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Proceedings
ARITH
ARITH 1987
Generate Citations
Computer Arithmetic, IEEE Symposium on
May 18 1987 to May 21 1987
Como, Italy Italy
ISBN: 0-8186-0774-2
Table of Contents
A design of time-optimum and register-number-minimum systolic convolver
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pp. 5-12
by
Hiroshi Umeo
Synthesis of area-efficient VLSI architectures for vector and matrix multiplication
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pp. 13-20
by
S. G. Smith
,
P. B. Denyer
Implementation of the single modulus complex ALU
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pp. 21-27
by
Rom-Shen Kao
,
Fred J. Taylor
Vector computations on an orthogonal memory access multiprocessing system
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pp. 28-37
by
Isaac D. Scherson
,
Yiming Ma
Structured arithmetic tiling of integrated circuits
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pp. 41-48
by
Tony M. Carter
Fast area-efficient VLSI adders
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pp. 49-56
by
Tackdon Han
,
David A. Carlson
Area-time efficient arithmetic elements for VLSI systems
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pp. 57-62
by
Ramautar Sharma
Parallel multipliers based on horizontal compressors
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pp. 63-69
by
Luigi Ciminiera
Algorithm for high speed shared radix 4 division and radix 4 square-root
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pp. 73-79
by
Jan Fandrianto
Design of high speed MOS multiplier and divider using redundant binary representation
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pp. 80-86
by
Shigeo Kuninobu
,
Tamotsu Nishiyama
,
Hisakazu Edamatsu
,
Takashi Taniguchi
,
Naofumi Takagi
Fast multiply and divide for a VLSI floating-point unit
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pp. 87-94
by
B. K. Bose
,
L. Pei
,
G. S. Taylor
,
D. A. Patterson
On the implementation of shifters, multipliers, and dividers in VLSI floating point units
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pp. 95-102
by
Victor Peng
,
Sridhar Samudrala
,
Moshe Gavrielov
The FELIN arithmetic coprocessor chip
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pp. 107-112
by
M. Cosnard
,
A. Guyot
,
B. Hochet
,
J.-M. Muller
,
H. Ouaouicha
,
P. Paul
,
E. Zysman
CORDIC arithmetic for an SVD processor
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pp. 113-120
by
Joseph R. Cavallaro
,
Franklin T. Luk
Evaluating elementary functions with Chebyshev polynomials on pipeline nets
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pp. 121-128
by
Kai Hwang
,
H.C. Wang
,
Z. Xu
Toward an ideal computer arithmetic
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pp. 131-138
by
T.E. Hull
,
M.S. Cohen
A closed computer arithmetic
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pp. 139-143
by
F. W. J. Olver
Implementation of level-index arithmetic using partial table look-up
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pp. 144-147
by
F. W. J. Olver
,
P. R. Turner
On error analysis in arithmetic with varying relative precision
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pp. 148-152
by
James W. Demmel
A new real number representation and its operation
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pp. 153-157
by
Hozumi Hamada
Systolic solution of linear systems over GF(p) with partial pivoting
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pp. 161-168
by
Bertrand Hochet
,
Patrice Quinton
,
Yves Robert
Systolic & semi-systolic digit serial multipliers
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pp. 169-173
by
Poras T. Balsara
,
Robert M. Owens
Systolic up/down counters with zero and sign detection
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pp. 174-178
by
Behrooz Parhami
A radix-4 on-line division algorithm
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pp. 181-187
by
Pad K.-G. Tu
,
Miloš D. Ercegovac
A novel floating-point online division algorithm
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pp. 188-195
by
Haixiang Lin
,
Henk J. Sips
On-line scheme for computing rotation factors
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pp. 196-203
by
Miloš D. Ercegovac
,
Tomas Lang
A bit-serial arithmetic unit for rational arithmetic
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pp. 204-211
by
Peter Kornerup
,
David W. Matula
A normalization algorithm for truncated p-adic arithmetic
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pp. 212-216
by
A. Colagrossi
,
A. Miola
Protecting convolution-type aritmetic array calculations with generalized cyclic codes
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pp. 219-225
by
G. Robert Redinbo
Error detection and correction for addition and subtraction, through use of higher radix extensions of hamming codes
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pp. 226-229
by
James E. Robertson
Fault-tolerant systolic arrays: An approach based upon residue arithmetic
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pp. 230-238
by
Vincenzo Piuri
A formal approach to rounding
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pp. 247-254
by
Geoff Barrett
The development of a floating-point validation package
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pp. 255-255
by
J. Du Croz
,
M. Pont
Arithmetic for vector processors
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pp. 256-269
by
R. Kirchner
,
U. Kulisch
Computer arithmetic and ill-conditioned algebraic problems
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pp. 270-276
by
Günter Schumacher
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