1. Home
  2. Proceedings
  3. ASAP
  4. ASAP 2000
Default Cover Image

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors

July 10 2000 to July 12 2000

Boston, Massachusetts

ISSN: 1063-6862

ISBN: 0-7695-0716-6

Table of Contents

Message from the Conference ChairsFreely available from IEEE.pp. ix
Conference OrganizersFreely available from IEEE.pp. x
Keynote
High-Performance Front-End Embedded Signal Processors for Adaptive Sensor ArraysFull-text access may be available. Sign in or learn about subscription options.pp. xiii
by W. Song
Video and Multimedia Processors, Chair: Jürgen Teich, Paderborn University
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 3
by Ruby B. Lee
Video and Multimedia Processors, Chair: Jürgen Teich, Paderborn University
Architecture of an Image Rendering Co-Processor for MPEG-4 SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 15
by M. Berekovic, P. Pirsch, T. Selinger, K. -I Wels, C. Miro, A. Lafage, C. Heer, G. Ghigo
Video and Multimedia Processors, Chair: Jürgen Teich, Paderborn University
A Multiplication-Free Parallel Architecture for Affine TransformationFull-text access may be available. Sign in or learn about subscription options.pp. 25
by Wael Badawy, Magdy Bayoumi
Video and Multimedia Processors, Chair: Jürgen Teich, Paderborn University
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 35
by M. Dal Poz, J. Aedo Cobo, W. Van Noije, M. Zuffo
Reconfigurable Computing, Chair: Doran Wilde, Brigham Young University
Formal Verification for Microprocessors with Extendable Instruction SetFull-text access may be available. Sign in or learn about subscription options.pp. 47
by Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube
Reconfigurable Computing, Chair: Doran Wilde, Brigham Young University
Compiling Image Processing Applications to Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 56
by Robert Rinker, Jeff Hammes, Walid A. Najjar, Wim Böhm, Bruce Draper
Reconfigurable Computing, Chair: Doran Wilde, Brigham Young University
Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia FunctionalityFull-text access may be available. Sign in or learn about subscription options.pp. 66
by Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh
Modeling and Synthesis, Chair: Shuvra Bhattacharyya, University of Maryland at College Park
High Level Modeling for Parallel Executions of Nested Loop AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 79
by Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, Bart Kienhuis
Modeling and Synthesis, Chair: Shuvra Bhattacharyya, University of Maryland at College Park
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 92
by Andrew Stone, Elias S. Manolakos
Modeling and Synthesis, Chair: Shuvra Bhattacharyya, University of Maryland at College Park
High Level Synthesis for Peak Power Minimization Using ILPFull-text access may be available. Sign in or learn about subscription options.pp. 103
by Wen-Tsong Shiue
Modeling and Synthesis, Chair: Shuvra Bhattacharyya, University of Maryland at College Park
High-Level Synthesis of Nonprogrammable Hardware AcceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 113
by Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott Mahlke, Santosh Abraham, Greg Snider
Cryptography, Chair: Ruby Lee, Princeton University
Implementing 1,024-Bit RSA Exponentiation on a 32-Bit Processor CoreFull-text access may be available. Sign in or learn about subscription options.pp. 127
by B.J. Phillips, N. Burgess
Cryptography, Chair: Ruby Lee, Princeton University
Bit Permutation Instructions for Accelerating Software CryptographyFull-text access may be available. Sign in or learn about subscription options.pp. 138
by Zhijie Shi, Ruby B. Lee
Cryptography, Chair: Ruby Lee, Princeton University
Performance-Scalable Array Architectures for Modular MultiplicationFull-text access may be available. Sign in or learn about subscription options.pp. 149
by William L. Freking, Keshab K. Parhi
Digital Signal Processing, Chair: Joseph Cavallaro, Rice University
A 108 Gbps, 1.5 GHz 1D-DCT ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 163
by Ahmed Shams, Magdy Bayoumi
Digital Signal Processing, Chair: Joseph Cavallaro, Rice University
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station ReceiversFull-text access may be available. Sign in or learn about subscription options.pp. 173
by Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang
Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and ProcessorsFreely available from IEEE.pp. iii-iii
Digital Signal Processing, Chair: Joseph Cavallaro, Rice University
A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum CommunicationFull-text access may be available. Sign in or learn about subscription options.pp. 185
by Naraig Manjikian
Digital Signal Processing, Chair: Joseph Cavallaro, Rice University
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-?m CMOS Viterbi DecoderFull-text access may be available. Sign in or learn about subscription options.pp. 195
by V.S. Gierenz, O. Weiss, T.G. Noll, I. Carew, J. Ashley, R. Karabed
Arithmetic,Chair: Magdy Bayoumi, University of Louisiana
A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional DelayFull-text access may be available. Sign in or learn about subscription options.pp. 205
by Marc Daumas, David W. Matula
Arithmetic,Chair: Magdy Bayoumi, University of Louisiana
A Hardware Algorithm for Variable-Precision LogarithmFull-text access may be available. Sign in or learn about subscription options.pp. 215
by Javier Hormigo, Julio Villalba, Michael J. Schulte
Arithmetic,Chair: Magdy Bayoumi, University of Louisiana
Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power ConsumptionFull-text access may be available. Sign in or learn about subscription options.pp. 225
by Lijun Gao, Keshab K. Parhi
Arithmetic,Chair: Magdy Bayoumi, University of Louisiana
A 16-Bit x 16-Bit MAC Design Using Fast 5:2 CompressorsFull-text access may be available. Sign in or learn about subscription options.pp. 235
by Ohsang Kwon, Earl E. Swartzlander, Kevin Nowka
Multiprocessor Systems, Chair: Ed Deprettere, Leiden University
Control for High-Speed PE ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 247
by Martin C. Herbordt, Honghai Zhang, Calvin Lin, Hong Rao, Jade Cravy
Multiprocessor Systems, Chair: Ed Deprettere, Leiden University
Explicit SIMD Programming for Asynchronous ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 258
by Andrea Di Blas, Richard Hughey
Multiprocessor Systems, Chair: Ed Deprettere, Leiden University
Quadratic Control Signals in Linear Systolic ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 268
by Scott Bowden, Doran Wilde, Sanjay Rajopadhye
Multiprocessor Systems, Chair: Ed Deprettere, Leiden University
Contention-Conscious Transaction Ordering in Embedded MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 276
by Mukul Khandelia, Shuvra S. Bhattacharyya
Application-Specific Architectures, Chair: Neil Burgess, Cardiff University
Architecture for Wavelet Packet Transform with Best Tree SearchingFull-text access may be available. Sign in or learn about subscription options.pp. 289
by Maria A. Trenas, Juan López, Manuel Sánchez, Emilio L. Zapata, Francisco Argüello
Application-Specific Architectures, Chair: Neil Burgess, Cardiff University
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software SorterFull-text access may be available. Sign in or learn about subscription options.pp. 299
by Marcus Bednara, Oliver Beyer, Juergen Teich, Rolf Wanka
Application-Specific Architectures, Chair: Neil Burgess, Cardiff University
A Programmable Processor for Approximate String Matching with High Throughput RateFull-text access may be available. Sign in or learn about subscription options.pp. 309
by Hans-Martin Blüthgen, Tobias Noll
Design Methodology, Chair: Elias Manolakos
A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic ProgrammingFull-text access may be available. Sign in or learn about subscription options.pp. 319
by H. Safiri, M. Ahmadi, G. A. Jullien, W. C. Miller
Design Methodology, Chair: Elias Manolakos
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 329
by R. Govindarajan, Erik R. Altman, Guang R. Gao
Design Methodology, Chair: Elias Manolakos
Partitioning Conditional Data Flow Graphs for Embedded System DesignFull-text access may be available. Sign in or learn about subscription options.pp. 339
by M. Auguin, L. Bianco, L. Capella, E. Gresset
Design Methodology, Chair: Elias Manolakos
Generation of Scheduling Functions Supporting LSGP-PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 349
by Dirk Fimmel
Design Methodology, Chair: Elias Manolakos
Author IndexFreely available from IEEE.pp. 359
Showing 38 out of 38