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2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)

July 23 2005 to July 25 2005

Samos, Greece

Table of Contents

Introduction
Message from the Conference ChairsFreely available from IEEE.pp. ix
Introduction
Conference OrganizersFreely available from IEEE.pp. xi
Session 5: Power Aware Systems & VLSI CAD
A low-power processor architecture optimized for wireless devicesFull-text access may be available. Sign in or learn about subscription options.pp. 185,186,187,188,189,190
Session 1: Codesign Specification and Synthesis
Expression synthesis in process networks generated by LAURAFull-text access may be available. Sign in or learn about subscription options.pp. 15,16,17,18,19,20,21
16th International Conference on Application-Specific Systems, Architecture and Processors - Table of contentsFreely available from IEEE.pp. v,vi,vii,viii
External refereesFreely available from IEEE.pp. xiii-xiii
Keynote
Area - time - power and design effort: the basic tradeoffs in application specific systemsFreely available from IEEE.pp. 3-6
by M.J. Flynn
Session 1: Codesign Specification and Synthesis
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 9-14
by Thomas Schlichter, Christian Haubelt, Frank Hannig, J?urgen Teich
Session 1: Codesign Specification and Synthesis
Artificial Deadlock Detection in Process Networks for ECLIPSEFull-text access may be available. Sign in or learn about subscription options.pp. 22-27
by Bharath. N, Nagaraju Bussa
Session 1: Codesign Specification and Synthesis
Hardware/Software Interface for Multi-Dimensional Processor ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 28-35
by Alain Darte, Steven Derrien, Tanguy Risset
Session 1: Codesign Specification and Synthesis
Casablanca II: Implementation of a Real-Time RISCFull-text access may be available. Sign in or learn about subscription options.pp. 36-42
by Kiyofumi Tanaka
Session 1: Codesign Specification and Synthesis
Behavioral speci.cation of control interface for signal processing applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 43-49
by Jerome Lemaitre, Sylvain Alliot, Ed Deprettere
Session 1: Codesign Specification and Synthesis
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 50-59
by M. D. Galanis, G. Dimitroulakos, C. E. Goutis
Session 1: Codesign Specification and Synthesis
A SW/Configware Codesign Methodology for Control Dominated ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 56-64
by K. Ben Chehida, M. Auguin
Session 2: (Special) System Level Soc Design
Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 65-72
by Samarjit Chakraborty
Session 2: (Special) System Level Soc Design
Communication-Centric SoC Design for Nanoscale DomainFull-text access may be available. Sign in or learn about subscription options.pp. 73-78
by Umit Y. Ogras, Jingcao Hu, Radu Marculescu
Session 2: (Special) System Level Soc Design
Using TLM for Exploring Bus-based SoC Communication ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 79-85
by Sudeep Pasricha, Mohamed Ben-Romdhane
Session 2: (Special) System Level Soc Design
Exploring Design Space of VLIW ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 86-91
by Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, Davide Patti
Session 2: (Special) System Level Soc Design
The Midlifekicker Microarchitecture Evaluation MetricFull-text access may be available. Sign in or learn about subscription options.pp. 92-100
by Stamatis Vassiliadis, Leonel Sousa, Georgi N. Gaydadjiev
Session 3: Applications
Design of a Hardware Accelerator for Density Based Clustering ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 101-106
by Jayaprakash Pisharath, Alok Choudhary
Session 3: Applications
Complex Fixed-Point Matrix Inversion Using Transport Triggered ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 107-112
by Adrian Burian, Perttu Salmela, Jarmo Takala
Session 3: Applications
A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering CoprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 113-118
by Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Yuan-Cheng Lai
Session 3: Applications
Eliminating Sorting in IP Lookup Devices using Partitioned TableFull-text access may be available. Sign in or learn about subscription options.pp. 119-126
by Enrico Ng, Gyungho Lee
Session 4: Architectures, ISA & Microarchitecture
Generating Efficient Custom FPGA Soft-Cores for Control-Dominated ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 127-133
by Ludovic L?Hours
Session 4: Architectures, ISA & Microarchitecture
Multiply-Accumulate Architecture for a Special Class of Optimal Extension FieldsFull-text access may be available. Sign in or learn about subscription options.pp. 134-139
by Moboluwaji O. Sanu, Earl E. Jr. Swartzlander
Session 4: Architectures, ISA & Microarchitecture
Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video EncodingFull-text access may be available. Sign in or learn about subscription options.pp. 140-145
by Nikolaos Kavvadias, Spiridon Nikolaidis
Session 4: Architectures, ISA & Microarchitecture
Instruction Set Architecture Enhancements for Video ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 146-153
by Jan-Willem van de Waerdt, Stamatis Vassiliadis
Session 4: Architectures, ISA & Microarchitecture
Instruction Set Customization of Application Speci.c Processors for Network Processing: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 154-160
by Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwaechter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
Session 4: Architectures, ISA & Microarchitecture
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 161-168
by Gregory Dimitroulakos, Michalis D. Galanis, Costas E. Goutis
Session 4: Architectures, ISA & Microarchitecture
Architectural Support for Accelerating Congestion Control Applications in Network ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 169-178
by Byeong Kil Lee, Lizy Kurian John, Eugene John
Session 5: Power Aware Systems & VLSI CAD
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 179-184
by Andy Lambrechts, Praveen Raghavan, Anthony Leroy, Guillermo Talavera, Tom Vander Aa, Murali Jayapala, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Fr?ed?eric Robert, Jordi Carrabina
Session 5: Power Aware Systems & VLSI CAD
CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 191-197
by Vida Kianzad, Shuvra S. Bhattacharyya, Gang Qu
Session 5: Power Aware Systems & VLSI CAD
Via-Aware Global Routing for Good VLSI Manufacturability and High YieldFull-text access may be available. Sign in or learn about subscription options.pp. 198-203
by Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qi Zhu, Xiaodong Hu, Guiying Yan
Session 5: Power Aware Systems & VLSI CAD
Virtual Hierarchical Design Representations for Distributed Optimization of Multi-Million Gate DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 204-212
by Thi Nguyen, Kaijian Shi
Session 6: (Special) Reconfigurable Computing
Zippy - A coarse-grained reconfigurable array with support for hardware virtualizationFull-text access may be available. Sign in or learn about subscription options.pp. 213-218
by Christian Plessl, Marco Platzner
Session 6: (Special) Reconfigurable Computing
An Image Processor for Digital FilmFull-text access may be available. Sign in or learn about subscription options.pp. 219-224
by Amilcar do Carmo Lucas, Rolf Ernst
Session 6: (Special) Reconfigurable Computing
On Estimations for Compiling Software to FPGA-based SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 225-230
by Jo?o M. P. Cardoso
Session 6: (Special) Reconfigurable Computing
A Programmable DSP Architecture for Wireless Communication SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 231-238
by Amir Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka
Session 6: (Special) Reconfigurable Computing
Customising Application-Speci.c Multiprocessor Systems: a Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 239-246
by Andreas Fidjeland, Wayne Luk
Session 7: (Special) Nanocomputing
Faults, Error Bounds and Reliability of Nanoelectronic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 247-253
by Jie Han, Erin Taylor, Jianbo Gao, Jos? Fortes
Session 7: (Special) Nanocomputing
Logic Models Supporting the Design of MOBILE-based RTD CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 254-259
by Mar?a J. Avedillo, Jos? M. Quintana, Hector Pettenghi
Session 7: (Special) Nanocomputing
CONAN - A Design Exploration Framework for Reliable Nano-ElectronicsFull-text access may be available. Sign in or learn about subscription options.pp. 260-267
by S. Cotofana, A. Schmid, Y. Leblebici, A. Ionescu, O. Soffke, P. Zipf, M. Glesner, A. Rubio
Session 7: (Special) Nanocomputing
Analytical approach to massively parallel architectures for nanotechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 268-275
by Bjorn Jager, Jorg Christian Niemann, Ulrich Ruckert
Session 7: (Special) Nanocomputing
On the Advantages of Serial Architectures for Low-Power Reliable ComputationsFull-text access may be available. Sign in or learn about subscription options.pp. 276-281
by V. Beiu, S. Aunet, J. Nyathi, R. R. III Rydberg, A. Djupdal
Session 7: (Special) Nanocomputing
Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 282-287
by PM Kelly, TM McGinnity, LP Maguire
Session 7: (Special) Nanocomputing
Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA)Full-text access may be available. Sign in or learn about subscription options.pp. 288-293
by K. Walus, Mazur, G. Schulhof, G. A. Jullien
Session 7: (Special) Nanocomputing
High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 294-302
by Cor Meenderinck, Sorin Cotofana, Casper Lageweg
Session 8: Arithmetic
Multiplication Algorithms for Radix-2 RN-Codings and Two?s Complement Multiplication Algorithms for Radix-2 RN-Codings and Two?s ComplementFull-text access may be available. Sign in or learn about subscription options.pp. 303-308
by Jean-Luc Beuchat, Jean-Michel Muller
Session 8: Arithmetic
Decimal Floating-Point Square Root Using Newton-Raphson IterationFull-text access may be available. Sign in or learn about subscription options.pp. 309-315
by Liang-Kai Wang, Michael J. Schulte
Session 8: Arithmetic
Variable Radix Real and Complex Digit-Recurrence DivisionFull-text access may be available. Sign in or learn about subscription options.pp. 316-321
by Milos D. Ercegovac, Jean-Michel Muller
Session 8: Arithmetic
On-line Multioperand Addition Based on On-line Full AddersFull-text access may be available. Sign in or learn about subscription options.pp. 322-327
by Julio Villalba, Javier Hormigo, Jose M. Prades, Emilio L. Zapata
Session 8: Arithmetic
Table-based polynomials for fast hardware function evaluationFull-text access may be available. Sign in or learn about subscription options.pp. 328-333
by Jeremie Detrey, Florent de Dinechin
Session 8: Arithmetic
Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of xFull-text access may be available. Sign in or learn about subscription options.pp. 334-342
by Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon
Session 9: Cryptography and Coding
Architectural Extensions for Elliptic Curve Cryptography over GF(2^m ) on 8-bit MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 343-349
by Hans Eberle, Arvinderpal Wander, Nils Gura, Sheueling Chang-Shantz, Vipul Gupta
Session 9: Cryptography and Coding
Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2^n )Full-text access may be available. Sign in or learn about subscription options.pp. 350-355
by Lejla Batina, Nele Mentens, Bart Preneel, Ingrid Verbauwhede
Session 9: Cryptography and Coding
On-Chip Lookup Tables for Fast Symmetric-Key EncryptionFull-text access may be available. Sign in or learn about subscription options.pp. 356-363
by A. Murat Fiskiran, Ruby B. Lee
Session 9: Cryptography and Coding
Instruction Set Extensions for Reed-Solomon Encoding and DecodingFull-text access may be available. Sign in or learn about subscription options.pp. 364-369
by Suman Mamidi, Daniel Iancu, Andrei Iancu, Michael J. Schulte, John Glossner
Session 9: Cryptography and Coding
256-State Rate 1/2 Viterbi Decoder on TTA ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 370-378
by Perttu Salmela, Tuomas Jarvinen, Teemu Sipila, Jarmo Takala
Session 10: Signal and Video Processing
Recursive Filtering on a Vector DSP with Linear SpeedupFull-text access may be available. Sign in or learn about subscription options.pp. 379-386
by M. Van Der Horst, K. Van Berkel, J Lukkien, R. Mak
Session 10: Signal and Video Processing
A Fault-Tolerant Modulus Replication Complex FIR FilterFull-text access may be available. Sign in or learn about subscription options.pp. 387-392
by Steiner, P. Chan, L. Imbert, G.A. Jullien, V.S. Dimitrov, G.H. McGibney
Session 10: Signal and Video Processing
Performance Comparison of SIMD Implementations of the Discrete Wavelet TransformFull-text access may be available. Sign in or learn about subscription options.pp. 393-398
by Asadollah Shahbahrami, Ben Juurlink, Stamatis Vassiliadis
Session 10: Signal and Video Processing
Real-time H/W Implementation of the Approximate Discrete Radon TransformFull-text access may be available. Sign in or learn about subscription options.pp. 399-404
by M. T. Frederick, N. A. VanderHorn,, A. K. Somani
Session 10: Signal and Video Processing
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip MultiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 405-410
by Tom R. Jacobs, Jose L. Nunez-Yanez
Session 10: Signal and Video Processing
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video CodecFull-text access may be available. Sign in or learn about subscription options.pp. 411-416
by Jos? L. N??ez-Y??ez,, Vassilios A. Chouliaras
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