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14th Asian Test Symposium (ATS'05)

Dec. 18 2005 to Dec. 21 2005

Calcutta

Table of Contents

Introduction
list-reviewerFreely available from IEEE.pp. xxii
14th Asian Test Symposium - Table of contentsFreely available from IEEE.pp. v,vi,vii,viii,ix,x,xi,xii,xiii,xiv
TTTC IntroductionFreely available from IEEE.pp. xxiv
TTEP IntroductionFreely available from IEEE.pp. xxvii
Introduction
ForewordFreely available from IEEE.pp. xv
Plenary Talk
Design for Testability: The Path to Deep SubmicronFull-text access may be available. Sign in or learn about subscription options.pp. xxxi
Banquet Speeches
DFT Aware Layout - Layout Aware DFTFull-text access may be available. Sign in or learn about subscription options.pp. xxxii
Banquet Speeches
Embedded Test Technology - Brief History, Current Status, and Future DirectionsFull-text access may be available. Sign in or learn about subscription options.pp. xxxiii
Invited Talks
Faults and Tests in Quantum CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. xxxiv
Invited Talks
Improving Logic Test Quality of MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. xxxv
Session A1: Analog and RF Testing: I
Robust Built-In Test of RF ICs Using Envelope DetectorsFull-text access may be available. Sign in or learn about subscription options.pp. 2-7
Session A1: Analog and RF Testing: I
Delay Defect Characterization Using Low Voltage TestFull-text access may be available. Sign in or learn about subscription options.pp. 8-13
Session A1: Analog and RF Testing: I
Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost TesterFull-text access may be available. Sign in or learn about subscription options.pp. 14-17
Session A1: Analog and RF Testing: I
IDDQ Testing Method using a Scan Pattern for Production TestingFull-text access may be available. Sign in or learn about subscription options.pp. 18-21
Session B1: Verification, On-line and Software Testing
An Efficient System-Level to RTL Verification Framework for Computation-Intensive ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 28-33
Session B1: Verification, On-line and Software Testing
Block-based Schema-driven Assertion Generation for Functional VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 34-39
Session B1: Verification, On-line and Software Testing
A Framework for Automatic Assembly Program Generator (A^2PG) for Verification and Testing of Processor CoresFull-text access may be available. Sign in or learn about subscription options.pp. 40-45
Session B1: Verification, On-line and Software Testing
The Automatic Generation of Basis Set of Path for Path TestingFull-text access may be available. Sign in or learn about subscription options.pp. 46-51
Session A2: Analog and RF Testing: II
Optimal Schemes for ADC BIST Based on HistogramFull-text access may be available. Sign in or learn about subscription options.pp. 52-57
Session A2: Analog and RF Testing: II
A 5 Gbps Wafer-Level TesterFull-text access may be available. Sign in or learn about subscription options.pp. 58-63
Session A2: Analog and RF Testing: II
Low-cost Production Test of BER for Wireless ReceiversFull-text access may be available. Sign in or learn about subscription options.pp. 64-69
Session A2: Analog and RF Testing: II
Design of a CMOS Operational Amplifier for Extreme-Voltage Stress TestFull-text access may be available. Sign in or learn about subscription options.pp. 70-75
Session B2: Self-Checking, On-line and Software Testing
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft ErrorsFull-text access may be available. Sign in or learn about subscription options.pp. 76-81
Session B2: Self-Checking, On-line and Software Testing
A State Machine for Detecting C/C++ Memory FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 82-87
Session B2: Self-Checking, On-line and Software Testing
On-Line Testing of Digital Circuits for n-Detect and Bridging Fault ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 88-93
Session B2: Self-Checking, On-line and Software Testing
Boundary Value Testing based on UML ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 94-99
Session A3: Interconnect Testing
Random Jitter Testing Using Low Tap-Count Delay LinesFull-text access may be available. Sign in or learn about subscription options.pp. 100-105
Session A3: Interconnect Testing
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia PrincipleFull-text access may be available. Sign in or learn about subscription options.pp. 106-111
Session A3: Interconnect Testing
A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 112-119
Session A3: Interconnect Testing
Non-robust Test Generation for Crosstalk-Induced Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 120-125
Session B3: BIST
Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BISTFull-text access may be available. Sign in or learn about subscription options.pp. 126-131
Session B3: BIST
Circuit Independent Weighted Pseudo-Random BIST Pattern GeneratorFull-text access may be available. Sign in or learn about subscription options.pp. 132-137
Session B3: BIST
Low Transition LFSR for BIST-Based ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 138-143
Session B3: BIST
A BIST Scheme Based on Selecting State Generation of Folding CountersFull-text access may be available. Sign in or learn about subscription options.pp. 144-149
Session A4: SoC Testing
Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 150-155
Session A4: SoC Testing
SOC Test Scheduling with Test Set Sharing and BroadcastingFull-text access may be available. Sign in or learn about subscription options.pp. 162-169
Session B4: Yield Enhancement
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter VariationsFull-text access may be available. Sign in or learn about subscription options.pp. 170-175
Session B4: Yield Enhancement
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAMFull-text access may be available. Sign in or learn about subscription options.pp. 176-181
Session B4: Yield Enhancement
Flash Memory Die Sort by a Sample Classification MethodFull-text access may be available. Sign in or learn about subscription options.pp. 182-187
Session B4: Yield Enhancement
Chip Identification using the Characteristic Dispersion of TransistorFull-text access may be available. Sign in or learn about subscription options.pp. 188-193
Session A5: Delay and Defect-Based Testing
Untestable Multi-Cycle Path Delay Faults in Industrial DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 194-201
Session A5: Delay and Defect-Based Testing
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch TransitionsFull-text access may be available. Sign in or learn about subscription options.pp. 202-207
Session A5: Delay and Defect-Based Testing
Selection of Paths for Delay TestingFull-text access may be available. Sign in or learn about subscription options.pp. 208-215
Session A5: Delay and Defect-Based Testing
On Improving Defect Coverage of Stuck-at Fault TestsFull-text access may be available. Sign in or learn about subscription options.pp. 216-223
Session B5: Low Power Testing
A Scan Matrix Design for Low Power Scan-Based TestFull-text access may be available. Sign in or learn about subscription options.pp. 224-229
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 230-235
Session B5: Low Power Testing
ISC: Reconfigurable Scan-Cell Architecture for Low Power TestingFull-text access may be available. Sign in or learn about subscription options.pp. 236-241
Session B5: Low Power Testing
Partial Gating Optimization for Power Reduction During Test ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 242-247
Session A6: Diagnosis, Delay, and Defect-Based Testing
Bridge Defect Diagnosis with Physical InformationFull-text access may be available. Sign in or learn about subscription options.pp. 248-253
Session A6: Diagnosis, Delay, and Defect-Based Testing
Design for Testability Based on Single-Port-Change Delay Testing for Data PathsFull-text access may be available. Sign in or learn about subscription options.pp. 254-259
Session A6: Diagnosis, Delay, and Defect-Based Testing
A Class of Linear Space Compactors for Enhanced DiagnosticFull-text access may be available. Sign in or learn about subscription options.pp. 260-265
Session A6: Diagnosis, Delay, and Defect-Based Testing
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage TestingFull-text access may be available. Sign in or learn about subscription options.pp. 266-271
Session B6: Test Generation and Fault Simulation
State-reuse Test Generation for Progressive Random Access Scan: Solution to Test Power, Application Time and Data SizeFull-text access may be available. Sign in or learn about subscription options.pp. 272-277
Session B6: Test Generation and Fault Simulation
Enhancing Fault Simulation Performance by Dynamic Fault ClusteringFull-text access may be available. Sign in or learn about subscription options.pp. 278-283
Session B6: Test Generation and Fault Simulation
Cost Optimal Design of Nonlinear CA based PRPG for Test ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 284-287
Session B6: Test Generation and Fault Simulation
An Effective Design for Hierarchical Test Generation Based on Strong TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 288-293
Session B6: Test Generation and Fault Simulation
Concurrent Test GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 294-299
Session A7: Design for Testability
Novel Bi-partitioned Scan Architecture to Improve Transition Fault CoverageFull-text access may be available. Sign in or learn about subscription options.pp. 300-305
Session A7: Design for Testability
A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault EfficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 306-311
Session A7: Design for Testability
Achieving High Test Quality with Reduced Pin Count TestingFull-text access may be available. Sign in or learn about subscription options.pp. 312-317
Session A7: Design for Testability
Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-FlopsFull-text access may be available. Sign in or learn about subscription options.pp. 318-323
Session B7: Test Compression and Compaction
Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan TestingFull-text access may be available. Sign in or learn about subscription options.pp. 324-329
Session B7: Test Compression and Compaction
Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection EfficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 330-336
Session B7: Test Compression and Compaction
Efficient Test Compaction for Pseudo-Random TestingFull-text access may be available. Sign in or learn about subscription options.pp. 337-342
Session B7: Test Compression and Compaction
Test Data Compression with Partial LFSR-ReseedingFull-text access may be available. Sign in or learn about subscription options.pp. 343-347
Session A8: Design for Testability: II
CryptoScan: A Secured Scan Chain ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 348-353
Session A8: Design for Testability: II
Pseudo-Parity Testing with Testable DesignFull-text access may be available. Sign in or learn about subscription options.pp. 354-359
Session A8: Design for Testability: II
Finite State Machine Synthesis for At-Speed Oscillation TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 360-365
Session A8: Design for Testability: II
A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 366-371
Session B8: Test Compression, Test Compaction, and Defect-Based Testing
Scan Data Volume Reduction Using Periodically Alterable MUXs DecompressorFull-text access may be available. Sign in or learn about subscription options.pp. 372-377
Session B8: Test Compression, Test Compaction, and Defect-Based Testing
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test RelaxationFull-text access may be available. Sign in or learn about subscription options.pp. 378-385
Session B8: Test Compression, Test Compaction, and Defect-Based Testing
Low Power Test Compression Technique for Designs with Multiple Scan ChainFull-text access may be available. Sign in or learn about subscription options.pp. 386-389
Session B8: Test Compression, Test Compaction, and Defect-Based Testing
Threshold testing: Covering bridging and other realistic faultsFull-text access may be available. Sign in or learn about subscription options.pp. 390-397
Session A9: Design for Testability: III
Synthesis of Testable Finite State Machine Through DecompositionFull-text access may be available. Sign in or learn about subscription options.pp. 398-403
Session A9: Design for Testability: III
Shannon Expansion Based Supply-Gated Logic for Improved Power and TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 404-409
Session A9: Design for Testability: III
Flip-flop chaining architecture for power-efficient scan during test applicationFull-text access may be available. Sign in or learn about subscription options.pp. 410-413
Session A9: Design for Testability: III
A Unified Approach to Partial Scan Design using Genetic AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 414-421
Session B9: Fault Modeling, Processor Testing, and Memory Testing
A Family of Logical Fault Models for Reversible CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 422-427
Session B9: Fault Modeling, Processor Testing, and Memory Testing
Compressing Functional Tests for MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 428-433
Session B9: Fault Modeling, Processor Testing, and Memory Testing
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 434-439
Session B9: Fault Modeling, Processor Testing, and Memory Testing
Arithmetic Test Strategy for FFT ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 440-443
Session B9: Fault Modeling, Processor Testing, and Memory Testing
Efficient Constraint Extraction for Template-Based Processor Self-Test GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 444-449
Session C1: SoC Test Practices
IEEE Std 1500 Compliant Infrastructure forModular SOC TestingFull-text access may be available. Sign in or learn about subscription options.pp. 450
Session C1: SoC Test Practices
DFT for Low Cost SOC TestFull-text access may be available. Sign in or learn about subscription options.pp. 451
Session C1: SoC Test Practices
Managing Test and Repair of Embedded Memory Subsystem in SoCFull-text access may be available. Sign in or learn about subscription options.pp. 452
Session C2: Defect-Based Testing
The Ultimate ChaseFull-text access may be available. Sign in or learn about subscription options.pp. 454
Session C2: Defect-Based Testing
Defect-Oriented Test for Ultra-Low DPMFull-text access may be available. Sign in or learn about subscription options.pp. 455
ATS 2006 Call for PapersFreely available from IEEE.pp. 476
Session C2: Defect-Based Testing
Current Testing for Nanotechnologies: A Demystifying Application Perspective.Full-text access may be available. Sign in or learn about subscription options.pp. 456
Session C4: Advances in Test Generation and Verification
High Level Test Generation for Custom Hardware: An Industrial PerspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 458
Session C4: Advances in Test Generation and Verification
High Level Test Generation / SW based Embedded TestFull-text access may be available. Sign in or learn about subscription options.pp. 459
Session C4: Advances in Test Generation and Verification
Verification of Industrial Designs Using A Computing Grid With More than 100 NodesFull-text access may be available. Sign in or learn about subscription options.pp. 460
Session C5: Test Data Compression and System Level Testing
Emerging Techniques for Test Data CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 462
Session C5: Test Data Compression and System Level Testing
Improving Test Quality Using Test Data CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 463
Session C5: Test Data Compression and System Level Testing
Efficient Test Architecture based on Boundary Scan for Comprehensive System TestFull-text access may be available. Sign in or learn about subscription options.pp. 464-465
Session C6: Mixed Signal Testing
Challenges in Next Generation Mixed-Signal IC Production TestingFull-text access may be available. Sign in or learn about subscription options.pp. 466
Session C6: Mixed Signal Testing
Practices in Testing of Mixed-Signal and RF SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 467
Session C6: Mixed Signal Testing
Challenges in High Speed Interface TestingFull-text access may be available. Sign in or learn about subscription options.pp. 468
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