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Design, Automation & Test in Europe Conference & Exhibition
Feb. 23 1998 to Feb. 26 1998
Paris, France
ISBN: 0-8186-8359-7
Table of Contents
Session 1A: Design Optimization of Building Blocks
Session 1A: Design Optimization of Building Blocks
Session 1A: Design Optimization of Building Blocks
Session 1B: HW/SW Partitioning and Communication Synthesis
Session 1B: HW/SW Partitioning and Communication Synthesis
Session 1B: HW/SW Partitioning and Communication Synthesis
Session 1C: Asynchronous and Hybrid VHDL-Based Design
Session 1C: Asynchronous and Hybrid VHDL-Based Design
Session 1C: Asynchronous and Hybrid VHDL-Based Design
Session 1D: Data Path and FPGA Testing
Session 1D: Data Path and FPGA Testing
Session 1D: Data Path and FPGA Testing
Session 2A: Design Methods for High Performance Applications
Session 2A: Design Methods for High Performance Applications
Session 2B: Scheduling in Embedded Systems
Session 2B: Scheduling in Embedded Systems
Session 2B: Scheduling in Embedded Systems
Session 2C: Advanced Techniques for VHDL Design
Session 2C: Advanced Techniques for VHDL Design
Session 2D: Novel BIST Approaches
Session 3A: Architectures for Image Processing
Session 3A: Architectures for Image Processing
Session 3A: Architectures for Image Processing
Session 3B: Scheduling and Analysis of HW/SW Systems
Session 3B: Scheduling and Analysis of HW/SW Systems
Session 3B: Scheduling and Analysis of HW/SW Systems
Session 3B: Scheduling and Analysis of HW/SW Systems
Session 3C: Extensions to VHDL
Session 3D: Error Detection and Design Validation
Session 3D: Error Detection and Design Validation
Session 3E: Hot Topic: IP Based System-on-a-Chip Design
Session 4A: Design Reuse Methodologies
Session 4A: Design Reuse Methodologies
Session 4A: Design Reuse Methodologies
Session 4B: Flat and Timing-Driven Processor Design
Session 4B: Flat and Timing-Driven Processor Design
Session 4B: Flat and Timing-Driven Processor Design
Session 4B: Flat and Timing-Driven Processor Design
Session 4C: Hot Topic: Reconfigurable Systems
Session 4D: Digital Simulation and Estimation
Session 4D: Digital Simulation and Estimation
Session 4D: Digital Simulation and Estimation
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Session 5B: Partitioning and Routing
Session 5B: Partitioning and Routing
Session 5C: Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
Session 5D: Simulation for High-Level Design
Session 5D: Simulation for High-Level Design
Session 5D: Simulation for High-Level Design
Session 6A: Architectural Synthesis
Session 6A: Architectural Synthesis
Session 6B: Timing and Crosstalk in Interconnect
Session 6B: Timing and Crosstalk in Interconnect
Session 6B: Timing and Crosstalk in Interconnect
Session 6C: Panel: Next Generation System Design Tools
Session 6D: IDDQ and Memory Testing
Session 6D: IDDQ and Memory Testing
Session 7A: Microsystems
Session 7B: Interconnect Modeling
Session 7B: Interconnect Modeling
Session 7C: Design for Manufacturability - Embedded Tutorial
Session 7C: Design for Manufacturability - Embedded Tutorial
Session 7C: Design for Manufacturability - Embedded Tutorial
Session 7D: Sequential Circuit Testing
Session 7D: Sequential Circuit Testing
Session 8A: Issues in Behavioral Synthesis