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Design, Automation & Test in Europe Conference & Exhibition

Feb. 23 1998 to Feb. 26 1998

Paris, France

ISBN: 0-8186-8359-7

Table of Contents

Proceedings Design, Automation and Test in EuropeFreely available from IEEE.pp. i-i
Event Steering BoardFull-text access may be available. Sign in or learn about subscription options.pp. xix
Conference Organizing CommitteeFreely available from IEEE.pp. xx
Programme Topic ChairsFreely available from IEEE.pp. xxi
Vendors CommitteeFreely available from IEEE.pp. xxii
Technical Programme CommitteeFreely available from IEEE.pp. xxiii
Welcome to DATE 98Freely available from IEEE.pp. xxvi
Keynote Addresses SummariesFreely available from IEEE.pp. xxvii
TutorialsFull-text access may be available. Sign in or learn about subscription options.pp. xxx
List of ReviewersFreely available from IEEE.pp. xxxiii
Session 1A: Design Optimization of Building Blocks
Collapsing the Transistor Chain to an Effective Single Equivalent TransistorFull-text access may be available. Sign in or learn about subscription options.pp. 2
Session 1A: Design Optimization of Building Blocks
Design of Fault-Secure Parity-Prediction Booth MultipliersFull-text access may be available. Sign in or learn about subscription options.pp. 7
Session 1A: Design Optimization of Building Blocks
PASTEL: A Parameterized Memory Characterization SystemFull-text access may be available. Sign in or learn about subscription options.pp. 15
Session 1B: HW/SW Partitioning and Communication Synthesis
Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS SystemFull-text access may be available. Sign in or learn about subscription options.pp. 22
Session 1B: HW/SW Partitioning and Communication Synthesis
Hardware Software Partitioning with Integrated Hardware Design Space ExplorationFull-text access may be available. Sign in or learn about subscription options.pp. 28
Session 1B: HW/SW Partitioning and Communication Synthesis
Generation of Interconnect Topologies for Communication SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 36
Session 1C: Asynchronous and Hybrid VHDL-Based Design
The Design of an Asynchronous VHDL SynthesizerFull-text access may be available. Sign in or learn about subscription options.pp. 44
Session 1C: Asynchronous and Hybrid VHDL-Based Design
Repartitioning and Technology-Mapping of Electronic Hybrid SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 52
Session 1C: Asynchronous and Hybrid VHDL-Based Design
VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive EngineeringFull-text access may be available. Sign in or learn about subscription options.pp. 59
Session 1D: Data Path and FPGA Testing
Scheduling and Module Assignment for Reducing Bist ResourcesFull-text access may be available. Sign in or learn about subscription options.pp. 66
Session 1D: Data Path and FPGA Testing
An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 74
Session 1D: Data Path and FPGA Testing
RAM-Based FPGA's: A Test Approach for the Configurable LogicFull-text access may be available. Sign in or learn about subscription options.pp. 82
Session 1D: Data Path and FPGA Testing
Novel Technique for Testing FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 89
Session 2A: Design Methods for High Performance Applications
ATM Traffic Shaper: ATSFull-text access may be available. Sign in or learn about subscription options.pp. 96
Session 2A: Design Methods for High Performance Applications
XFVHDL: A Tool for the Synthesis of Fuzzy Logic ControllersFull-text access may be available. Sign in or learn about subscription options.pp. 102
Session 2A: Design Methods for High Performance Applications
High Speed Neural Network Chip for Trigger Purposes in High Energy PhysicsFull-text access may be available. Sign in or learn about subscription options.pp. 108
Session 2B: Scheduling in Embedded Systems
CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 118
Session 2B: Scheduling in Embedded Systems
Stream Communication between Real-Time Tasks in a High-Performance MultiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 125
Session 2B: Scheduling in Embedded Systems
Scheduling of Conditional Process Graphs for the Synthesis of Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 132
Session 2C: Advanced Techniques for VHDL Design
Model Abstraction for Formal VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 140
Session 2C: Advanced Techniques for VHDL Design
VHDL Modelling and Analysis of Fault Secure SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 148
Session 2C: Advanced Techniques for VHDL Design
Register Transfer Level VHDL Models without ClocksFull-text access may be available. Sign in or learn about subscription options.pp. 153
Session 2C: Advanced Techniques for VHDL Design
Parallel VHDL SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 159
Session 2D: Novel BIST Approaches
Testing DSP Cores Based on Self-Test ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 166
Session 2D: Novel BIST Approaches
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMsFull-text access may be available. Sign in or learn about subscription options.pp. 173
Session 2D: Novel BIST Approaches
Built-In Self-Test with an Alternating OutputFull-text access may be available. Sign in or learn about subscription options.pp. 180
Session 3A: Architectures for Image Processing
From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 186
Session 3A: Architectures for Image Processing
Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia CommunicationsFull-text access may be available. Sign in or learn about subscription options.pp. 191
Session 3A: Architectures for Image Processing
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet TransformFull-text access may be available. Sign in or learn about subscription options.pp. 196
Session 3B: Scheduling and Analysis of HW/SW Systems
A Model for System-Level Timed Analysis and ProfilingFull-text access may be available. Sign in or learn about subscription options.pp. 204
Session 3B: Scheduling and Analysis of HW/SW Systems
Efficient Compilation of Process-Based Concurrent Programs without Run-Time SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 211
Session 3B: Scheduling and Analysis of HW/SW Systems
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning ProcessFull-text access may be available. Sign in or learn about subscription options.pp. 218
Session 3B: Scheduling and Analysis of HW/SW Systems
A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 226
Session 3C: Extensions to VHDL
Object-Oriented Modelling of Parallel Hardware SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 234
Session 3C: Extensions to VHDL
A Flexible Message Passing Mechanism for Objective VHDLFull-text access may be available. Sign in or learn about subscription options.pp. 242
Session 3C: Extensions to VHDL
Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDLFull-text access may be available. Sign in or learn about subscription options.pp. 250
Session 3C: Extensions to VHDL
Formal Specification in VHDL for Hardware VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 257
Session 3D: Error Detection and Design Validation
A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data PathsFull-text access may be available. Sign in or learn about subscription options.pp. 266
Session 3D: Error Detection and Design Validation
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 273
Session 3D: Error Detection and Design Validation
Functional Scan Chain TestingFull-text access may be available. Sign in or learn about subscription options.pp. 278
Session 3E: Hot Topic: IP Based System-on-a-Chip Design
Design Methodologies for System Level IPFull-text access may be available. Sign in or learn about subscription options.pp. 286
Session 3E: Hot Topic: IP Based System-on-a-Chip Design
IP-Based System-on-a-Chip DesignFull-text access may be available. Sign in or learn about subscription options.pp. 290
Session 4A: Design Reuse Methodologies
A Systematic Analysis of Reuse Strategies for Design of Electronic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 292
Session 4A: Design Reuse Methodologies
VHDL Teamwork, Organization Units and Workspace ManagementFull-text access may be available. Sign in or learn about subscription options.pp. 297
Session 4A: Design Reuse Methodologies
An Object-Oriented Model for Specification, Prototyping, Implementation and ReuseFull-text access may be available. Sign in or learn about subscription options.pp. 303
Session 4B: Flat and Timing-Driven Processor Design
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor ChipsetFull-text access may be available. Sign in or learn about subscription options.pp. 312
Session 4B: Flat and Timing-Driven Processor Design
Algorithms for Detailed Placement of Standard CellsFull-text access may be available. Sign in or learn about subscription options.pp. 321
Session 4B: Flat and Timing-Driven Processor Design
Timing Analysis and Optimization of a High-Performance CMOS Processor ChipsetFull-text access may be available. Sign in or learn about subscription options.pp. 325
Session 4B: Flat and Timing-Driven Processor Design
A Sequential Detailed Router for Huge Grid GraphsFull-text access may be available. Sign in or learn about subscription options.pp. 332
Session 4C: Hot Topic: Reconfigurable Systems
Reconfigurable Logic for Systems on a ChipFull-text access may be available. Sign in or learn about subscription options.pp. 340
Session 4C: Hot Topic: Reconfigurable Systems
An Energy-Conscious Exploration Methodology for Reconfigurable DSPsFull-text access may be available. Sign in or learn about subscription options.pp. 341
Silicon debug of systems-on-chips [session introduction]Full-text access may be available. Sign in or learn about subscription options.pp. 632-633
Session 4C: Hot Topic: Reconfigurable Systems
Design Of Future SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 343
Session 4D: Digital Simulation and Estimation
AFTA: A Formal Delay Model for Functional Timing AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 350
Session 4D: Digital Simulation and Estimation
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-OffsFull-text access may be available. Sign in or learn about subscription options.pp. 356
Session 4D: Digital Simulation and Estimation
Advanced Optimistic Approaches in Logic SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 362
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
PSCP: A Scalable Parallel ASIP Architecture for Reactive SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 370
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
A Constraint Driven Approach to Loop Pipelining and Register BindingFull-text access may be available. Sign in or learn about subscription options.pp. 377
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Multiple Behavior Module Synthesis Based on Selective GroupingsFull-text access may be available. Sign in or learn about subscription options.pp. 384
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Optimal Temporal Partitioning and Synthesis for Reconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 389
Session 5B: Partitioning and Routing
An Effective General Connectivity Concept for ClusteringFull-text access may be available. Sign in or learn about subscription options.pp. 398
Session 5B: Partitioning and Routing
Improved Approximation Bounds for the Group Steiner ProblemFull-text access may be available. Sign in or learn about subscription options.pp. 406
Session 5B: Partitioning and Routing
An Interactive Router for Analog IC DesignFull-text access may be available. Sign in or learn about subscription options.pp. 414
Session 5C: Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
Formal Verification: A New Standard CAD Tool for the Industrial Design FlowFull-text access may be available. Sign in or learn about subscription options.pp. 422
Session 5D: Simulation for High-Level Design
A System-Level Co-Verification Environment for ATM Hardware DesignFull-text access may be available. Sign in or learn about subscription options.pp. 424
Session 5D: Simulation for High-Level Design
FRIDGE: A Fixed-Point Design and Simulation EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 429
Session 5D: Simulation for High-Level Design
Verification by Simulation Comparison using Interface SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 436
Session 6A: Architectural Synthesis
Layout-Driven High Level Synthesis for FPGA Based ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 446
Session 6A: Architectural Synthesis
Cross-Level Hierarchical High-Level SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 451
Session 6A: Architectural Synthesis
An Algorithm To Determine Mutually Exclusive Operations In Behavioral DescriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 457
Session 6B: Timing and Crosstalk in Interconnect
A Performance-Driven MCM Router with Special Consideration of Crosstalk ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 466
Session 6B: Timing and Crosstalk in Interconnect
Interconnect Tuning Strategies for High-Performance IcsFull-text access may be available. Sign in or learn about subscription options.pp. 471
Session 6B: Timing and Crosstalk in Interconnect
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire SizingFull-text access may be available. Sign in or learn about subscription options.pp. 479
Session 6C: Panel: Next Generation System Design Tools
Next Generation System Level Design ToolsFull-text access may be available. Sign in or learn about subscription options.pp. 488
Session 6D: IDDQ and Memory Testing
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICsFull-text access may be available. Sign in or learn about subscription options.pp. 490
Session 6D: IDDQ and Memory Testing
A Fully Digital Controlled Off-Chip IDDQ Measurement UnitFull-text access may be available. Sign in or learn about subscription options.pp. 495
Session 6D: IDDQ and Memory Testing
March Tests for Word-Oriented MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 501
Session 7A: Microsystems
A Modeling Approach to Include Mechanical Microsystem Components into the System SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 510
Session 7A: Microsystems
Fast Field Solvers for Thermal and Electrostatic AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 518
Session 7A: Microsystems
Microsystems Testing: an Approach and Open ProblemsFull-text access may be available. Sign in or learn about subscription options.pp. 524
Session 7B: Interconnect Modeling
Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade ApproximationFull-text access may be available. Sign in or learn about subscription options.pp. 530
Session 7B: Interconnect Modeling
An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 538
Session 7B: Interconnect Modeling
MCM Interconnect Design Using Two-Pole ApproximationFull-text access may be available. Sign in or learn about subscription options.pp. 544
Session 7C: Design for Manufacturability - Embedded Tutorial
Design-Manufacturing Interface: Part I - VisionFull-text access may be available. Sign in or learn about subscription options.pp. 550
Session 7C: Design for Manufacturability - Embedded Tutorial
Design-Manufacturing Interface: Part II - ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 557
Session 7C: Design for Manufacturability - Embedded Tutorial
Performance - Manufacturability Tradeoffs in IC DesignFull-text access may be available. Sign in or learn about subscription options.pp. 563
Fast sequential circuit test generation using high-level and gate-level techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 570-576
Session 7D: Sequential Circuit Testing
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 577
Session 7D: Sequential Circuit Testing
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector RestorationFull-text access may be available. Sign in or learn about subscription options.pp. 583
Session 8A: Issues in Behavioral Synthesis
Architectural Simulation in the Context of Behavioral SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 590
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