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2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

April 11 2007 to April 13 2007

Krakow

Table of Contents

Logic Diagnosis and Yield LearningFreely available from IEEE.
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Copyright pageFreely available from IEEE.pp. 3
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Foreword to the IEEE DDECS 2007 WorkshopFreely available from IEEE.pp. 4
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Workshop CommitteesFreely available from IEEE.pp. 5-6
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Table of contentsFreely available from IEEE.pp. 7-12
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A Testable Random Bit Generator based on a High Resolution Phase Noise DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
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Test Pattern Compression Based on Pattern OverlappingFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Layout to Logic Defect Analysis for Hierarchical Test GenerationFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Design Platform for Quick Integration of an Internet Connectivity into System-on-ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
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Resource Constrained Co-synthesis of Self-reconfigurable SOPCsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Extended Fault Detection Techniques for Systems-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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A Heuristic for Concurrent SOC Test Scheduling with Compression and SharingFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Memories in Scaled technologies: A Review of Process Induced Failures, Test methodologies, and Fault ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Architecture for Highly Reliable Embedded Flash MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Accurately Determining Bridging Defects from LayoutFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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FPGA Implementaton of Strongly Parallel Histogram EqualizationFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA'sFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 EncoderFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double SamplingFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
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A PMT interface for the Optical Module front-end of a neutrino underwater telescopeFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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A proposal for ASM++ diagramsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Automatic generation of circuits for approximate string matchingFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Lightweight Multi-threaded Network Processor Core in FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
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Parts Obsolescence Challenges for the Electronics IndustryFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Clockless Implementation of LEON2 for Low-Power ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Two-Level Logic Synthesis for Low Power Based on New Model of Power DissipationFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Avoiding Crosstalk Influence on Interconnect Delay Fault TestingFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Power Dissipation in Basic Global Clock Distribution NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Instance Generation for SAT-based ATPGFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Power Testing of an FPGA based System Using Modelsim Code Coverage capabilityFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Built in Defect Prognosis for Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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March CRF: an Efficient Test for Complex Read Faults in SRAM MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Manifestation of Precharge Faults in High Speed DRAM DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and RepairFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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An Improved MDCT IP Core Generator with Architectural Model SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded SystemFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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About the Efficiency of Real Time Sequences FFT ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Decomposition of Logic Functions in Reed-Muller Spectral DomainFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Establishing a New Course in Reconfigurable Logic System DesignFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Partitioning Optimization by Recursive Moves of Hierarchically Built ClustersFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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A Mixed Approach for Unified Logic DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Feasibility of Image Compression in FPGA based Neural NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
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Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic GatesFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Quadrature-Phase Topology of a High Frequency Ring OscillatorFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Multiple Errors Detection Technique for RAMFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Test Pattern Generator for Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Low cost, low power, intelligent brake temperature sensor system for automotive applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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A Novel Parity Bit Scheme for SBox in AES CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
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Designing Time-to-Digital Converter for Asynchronous ADCsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Algorithm for DRM Signal Recognition in Time Domain and Hardware RealizationFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
Intrusion Detection System Intended for Multigigabit NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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RF Transformer Model Parameters MeasurementFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-Micron Integrated CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Transition Faults Testing Based on Functional Delay TestsFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
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Flip-Flops and Scan-Path Elements for NanoelectronicsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Dedicated architecture for double precision matrix multiplication in supercomputing environmentFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Design issues of a low frequency low-pass filter for medical applications using CMOS technologyFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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IP Integration Overhead Analysis in System-on-Chip Video EncoderFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Reticle Exposure Plans for Multi-Project WafersFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Determining MOSFET Parameters in Moderate InversionFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Evolutionary System for Analog Test Frequencies Selection with Fuzzy InitializationFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
TTTC: Test Technology Technical CouncilFreely available from IEEE.
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Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex SystemFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Prototyping Generators for on-line test vector generation based on PSL propertiesFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid AutomataFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Debug Patterns for Efficient High-level SystemC DebuggingFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Memory Based Analogue Signal Generation Implementation Issues for BISTFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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Developing Virtual ADC Testing Environment in MAPLEFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
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ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line PulsingFull-text access may be available. Sign in or learn about subscription options.pp. 1-5
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MEMS Testing by Vibrating CapacitorFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
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Author IndexFreely available from IEEE.pp. 433-434
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