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Proceedings
DDECS
DDECS 2007
Generate Citations
2007 IEEE Design and Diagnostics of Electronic Circuits and Systems
April 11 2007 to April 13 2007
Krakow
Table of Contents
New Strategies for System-Level Design
Freely available from IEEE.
by
D.D. Gajski
Design and Test of Microfluidic Biochips
Freely available from IEEE.
by
K. Chakrabarty
Logic Diagnosis and Yield Learning
Freely available from IEEE.
by
J. Rajski
Papers
Copyright page
Freely available from IEEE.
pp. 3
Papers
Foreword to the IEEE DDECS 2007 Workshop
Freely available from IEEE.
pp. 4
Papers
Workshop Committees
Freely available from IEEE.
pp. 5-6
Papers
Table of contents
Freely available from IEEE.
pp. 7-12
Papers
A Testable Random Bit Generator based on a High Resolution Phase Noise Detection
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pp. 1-5
by
Marco Bucci
,
Raimondo Luzzi
Papers
Test Pattern Compression Based on Pattern Overlapping
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pp. 1-6
by
Jiri Jenicek
,
Ondrej Novak
Papers
Layout to Logic Defect Analysis for Hierarchical Test Generation
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pp. 1-6
by
Maksim Jenihhin
,
Jaan Raik
,
Raimund Ubar
,
Witold A. Pleskacz
,
Michal Rakowski
Papers
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips
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pp. 1-5
by
Bartosz Wojciechowski
,
Tomasz Kowalczyk
,
Wojciech Sakowski
Papers
Resource Constrained Co-synthesis of Self-reconfigurable SOPCs
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pp. 1-6
by
Radoslaw Czarnecki
,
Stanislaw Deniziak
Papers
Extended Fault Detection Techniques for Systems-on-Chip
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pp. 1-6
by
P. Bernardi
,
L. Bolzani
,
M. Sonza Reorda
Papers
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
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pp. 1-6
by
Anders Larsson
,
Erik Larsson
,
Petru Eles
,
Zebo Peng
Papers
Memories in Scaled technologies: A Review of Process Induced Failures, Test methodologies, and Fault Tolerance
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pp. 1-6
by
Saibal Mukhopadhyay
,
Qikai Chen
,
Kaushik Roy
Papers
Architecture for Highly Reliable Embedded Flash Memories
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pp. 1-6
by
Benoit Godard
,
Jean-Michel Daga
,
Lionel Torres
,
Gilles Sassatelli
Papers
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology
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pp. 1-6
by
Zhicheng Liang
,
Makoto Ikeda
,
Kunihiro Asada
XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in both Defective and Defect-free Interconnects
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pp. 1-4
by
Ajoy K. Palit
,
Kishore K. Duganapalli
,
Walter Anheier
Papers
Accurately Determining Bridging Defects from Layout
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pp. 1-4
by
Maria Gkatziani
,
Rohit Kapur
,
Qing Su
,
Ben Mathew
,
Roberto Mattiuzzo
,
Laura Tarantini
,
Cy Hay
,
Salvatore Talluto
,
T. W. Williams
Papers
FPGA Implementaton of Strongly Parallel Histogram Equalization
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pp. 1-6
by
Ernest Jamro
,
Maciej Wielgosz
,
Kazimierz Wiatr
Papers
Cost-Efficient Synthesis for Sequential Circuits Implemented Using Embedded Memory Blocks of FPGA's
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pp. 1-6
by
Grzegorz Borowik
,
Bogdan Falkowski
,
Tadeusz Luba
Papers
Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder
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pp. 1-6
by
Ari Kulmala
,
Erno Salminen
,
Timo D. Hamalainen
Papers
A Low Noise and Low Power CMOS Image Sensor with Pixel-level Correlated Double Sampling
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pp. 1-3
by
Dongsoo Kim
,
Gunhee Han
Papers
A PMT interface for the Optical Module front-end of a neutrino underwater telescope
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pp. 1-4
by
V. Sipala
,
D. Lo Presti
,
N. Randazzo
,
L. Caponetto
Papers
A proposal for ASM++ diagrams
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pp. 1-4
by
Santiago de Pablo
,
Santiago Caceres
,
Jesus A. Cebrian
,
Manuel Berrocal
Automatic generation of circuits for approximate string matching
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pp. 1-6
by
Tomas Martinek
,
Otto Fucik
,
Patrik Beck
,
Matej Lexa
Papers
Lightweight Multi-threaded Network Processor Core in FPGA
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pp. 1-5
by
Piotr Buciak
,
Jakub Botwicz
Papers
Parts Obsolescence Challenges for the Electronics Industry
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pp. 1-4
by
Jim Torresen
,
Thor Arne Lovland
Clockless Implementation of LEON2 for Low-Power Applications
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pp. 1-4
by
Martin Simlastik
,
Viera Stopjakova
,
Libor Majer
,
Peter Malik
Papers
Simulation and Characterization of Wireless Data Acquisition RF Systems for Medical Diagnostic Application
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pp. 1-4
by
K. Arshak
,
F. Adepoju
,
E. Jafer
Papers
Two-Level Logic Synthesis for Low Power Based on New Model of Power Dissipation
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pp. 1-6
by
I. Brzozowski
,
A. Kos
Papers
A March-Based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories
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pp. 1-4
by
G. Harutunyan
,
V.A. Vardanian
,
Y. Zorian
Papers
Avoiding Crosstalk Influence on Interconnect Delay Fault Testing
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pp. 1-4
by
T. Garbolino
,
K. Gucwa
,
M. Kopec
,
A. Hlawiczka
Power Dissipation in Basic Global Clock Distribution Networks
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pp. 1-4
by
Artur L. Sobczyk
,
Arkadiusz W. Luczyk
,
Witold A. Pleskacz
Papers
Instance Generation for SAT-based ATPG
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pp. 1-4
by
Daniel Tille
,
Gorschwin Fey
,
Rolf Drechsler
Papers
Power Testing of an FPGA based System Using Modelsim Code Coverage capability
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pp. 1-4
by
Khalil Arshak
,
Essa Jafer
,
Christian Ibala
Papers
Built in Defect Prognosis for Embedded Memories
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pp. 1-6
by
Prashant Dubey
,
Akhil Garg
,
Sravan Kumar Bhaskarani
Papers
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories
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pp. 1-6
by
Luigi Dilillo
,
Bashir M. Al-Hashimi
Papers
Manifestation of Precharge Faults in High Speed DRAM Devices
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pp. 1-6
by
Zaid Al-Ars
,
Said Hamdioui
,
Georgi Gaydadjiev
Papers
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
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pp. 1-6
by
Philipp Ohler
,
Sybille Hellebrand
,
Hans-Joachim Wunderlich
Papers
An Improved MDCT IP Core Generator with Architectural Model Simulation
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pp. 1-6
by
Peter Malik
,
Marcel Balaz
,
Tomas Pikula
,
Martin Simlastik
Papers
A Low-Power High-Speed Hybrid CMOS Full Adder for Embedded System
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pp. 1-4
by
Chiou-Kou Tung
,
Yu-Cherng Hung
,
Shao-Hui Shieh
,
Guo-Shing Huang
Papers
About the Efficiency of Real Time Sequences FFT Computing
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pp. 1-4
by
Costin Cepisca
,
Sorin Dan Grigorescu
,
Mircea Covrig
,
Horia Andrei
Papers
Decomposition of Logic Functions in Reed-Muller Spectral Domain
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pp. 1-4
by
Edward Hrynkiewicz
,
Stefan Kolodzinski
A Framework for Self-Healing Radiation-Tolerant Implementations on Reconfigurable FPGAs
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pp. 1-6
by
Manuel G. Gericota
,
Luis F. Lemos
,
Gustavo R. Alves
,
Jose M. Ferreira
Papers
Design of Addition and Multiplication Units for High Performance Interval Arithmetic Processor
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pp. 1-4
by
Alexandru Amaricai
,
Mircea Vladutiu
,
Lucian Prodan
,
Mihai Udrescu
,
Oana Boncalo
Papers
Establishing a New Course in Reconfigurable Logic System Design
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pp. 1-4
by
Jim Torresen
,
Jorgen Norendal
,
Kyrre Glette
Proposal of VLIW Architecture for Application Specific Processors with Built-in-Self-Repair facility via Variable Accuracy Arithmetic
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pp. 1-6
by
Pawel Pawlowski
,
Adam Dabrowski
,
Mario Scholzel
Papers
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters
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pp. 1-4
by
Roman Bazylevych
,
Ihor Podolskyy
,
Lubov Bazylevych
Papers
A Mixed Approach for Unified Logic Diagnosis
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pp. 1-4
by
A. Rousset
,
A. Bosio
,
P. Girard
,
C. Landrault
,
S. Pravossoudovitch
,
A. Virazel
Feasibility of Image Compression in FPGA based Neural Networks
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pp. 1-3
by
Vladimir Havel
,
Karel Vlcek
Papers
Design and Analysis of a New Self-Testing Adder Which Utilizes Polymorphic Gates
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pp. 1-4
by
Lukas Sekanina
Papers
A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services
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pp. 1-4
by
M.H Neishaburi
,
Mohammad Reza Kakoee
,
M. Daneshtalab
,
Saeed Safari
,
Zainalabedin Navabi
Quadrature-Phase Topology of a High Frequency Ring Oscillator
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pp. 1-4
by
Abel Vamos
Papers
Multiple Errors Detection Technique for RAM
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pp. 1-4
by
S.B. Musin
,
A.A. Ivaniuk
,
V.N. Yarmolik
Papers
Test Pattern Generator for Delay Faults
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pp. 1-4
by
T. Rudnicki
,
A. Hlawiczka
Low cost, low power, intelligent brake temperature sensor system for automotive applications
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pp. 1-4
by
Gyula Bakonyi-Kiss
,
Zoltan Szucs
Papers
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques
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pp. 1-6
by
O. Ruano
,
P. Reyes
,
J.A. Maestro
,
L. Sterpone
,
P. Reviriego
Papers
A Novel Parity Bit Scheme for SBox in AES Circuits
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pp. 1-5
by
G. Di Natale
,
M. L. Flottes
,
B. Rouzeyre
Papers
Designing Time-to-Digital Converter for Asynchronous ADCs
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pp. 1-6
by
Dariusz Koscielnik
,
Marek Miskowicz
Papers
Algorithm for DRM Signal Recognition in Time Domain and Hardware Realization
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pp. 1-6
by
Lukas Ruckay
,
Jiri Nedved
Intrusion Detection System Intended for Multigigabit Networks
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pp. 1-4
by
Jan Korenek
,
Petr Kobiersky
Papers
RF Transformer Model Parameters Measurement
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pp. 1-5
by
V. Dumbrava
,
L. Svilainis
Open Defects Caused by Scratches and Yield Modelling in Deep Sub-Micron Integrated Circuit
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pp. 1-4
by
Wlodzimierz Jonca
Papers
Improving Tolerance to Power-Supply and Temperature Variations in Synchronous Circuits
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pp. 1-6
by
J. Semiao
,
J. Freijedo
,
J. J. Rodriguez-Andina
,
F. Vargas
,
M. B. Santos
,
I. C. Teixeira
,
J. P. Teixeira
Transition Faults Testing Based on Functional Delay Tests
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pp. 1-5
by
Eduardas Bareisa
,
Vacius Jusas
,
Kestutis Motiejunas
,
Rimantas Seinauskas
Papers
Flip-Flops and Scan-Path Elements for Nanoelectronics
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pp. 1-6
by
R. Kothe
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H. T. Vierhaus
Papers
Dedicated architecture for double precision matrix multiplication in supercomputing environment
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pp. 1-4
by
P. Russek
,
K. Wiatr
Papers
Design issues of a low frequency low-pass filter for medical applications using CMOS technology
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pp. 1-4
by
Andras Timar
,
Marta Rencz
Papers
IP Integration Overhead Analysis in System-on-Chip Video Encoder
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pp. 1-4
by
Antti Rasmus
,
Ari Kulmala
,
Erno Salminen
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Timo D. Hamalainen
Papers
Reticle Exposure Plans for Multi-Project Wafers
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pp. 1-4
by
Rung-Bin Lin
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Da-Wei Hsu
,
Ming-Hsine Kuo
,
Meng-Chiou Wu
Papers
Determining MOSFET Parameters in Moderate Inversion
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pp. 1-4
by
Matthias Bucher
,
Antonios Bazigos
,
Wladyslaw Grabinski
Papers
Evolutionary System for Analog Test Frequencies Selection with Fuzzy Initialization
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pp. 1-4
by
T. Golonek
,
D. Grzechca
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J. Rutkowski
TTTC: Test Technology Technical Council
Freely available from IEEE.
Papers
Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System
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pp. 1-4
by
Pavel Kubalik
,
Jiri Kvasnicka
,
Hana Kubatova
Papers
Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits
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pp. 1-6
by
Aristides Efthymiou
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Prototyping Generators for on-line test vector generation based on PSL properties
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pp. 1-6
by
Yann Oddos
,
Katell Morin-Allory
,
Dominique Borrione
Papers
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata
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pp. 1-6
by
Marc Herbstritt
,
Bernd Becker
,
Erika Abraham
,
Christian Herde
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SAT-Based Equivalence Checking Based on Circuit Partitioning and Special Approaches for Conflict Clause Reuse
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pp. 1-6
by
Fabricio V. Andrade
,
Marcia C. M. Oliveira
,
Antonio O. Fernandes
,
Claudionor Jose N. Coelho
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Debug Patterns for Efficient High-level SystemC Debugging
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pp. 1-6
by
Frank Rogin
,
Erhard Fehlauer
,
Christian Haufe
,
Sebastian Ohnewald
Papers
Memory Based Analogue Signal Generation Implementation Issues for BIST
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pp. 1-6
by
T. O. Shea
,
I. Grout
,
J. Ryan
Papers
Developing Virtual ADC Testing Environment in MAPLE
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pp. 1-5
by
Petr Struhovsky
,
Ondrej Subrt
,
Jiri Hospodka
,
Pravoslav Martinek
Papers
ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing
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pp. 1-5
by
Z. Piatek
,
J. F. Kolodziejski
,
W. A. Pleskacz
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MEMS Testing by Vibrating Capacitor
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pp. 1-4
by
J. Mizsei
,
M. Reggente
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Author Index
Freely available from IEEE.
pp. 433-434
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