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2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems

Apr. 15 2009 to Apr. 17 2009

Liberec, Czech Republic

ISBN: 978-1-4244-3341-4

Table of Contents

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[Copyright notice]Freely available from IEEE.pp. ii
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Symposium CommitteesFreely available from IEEE.pp. iv
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Table of contentsFreely available from IEEE.pp. v-ix
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Foreword to the 12th IEEE DDECS symposiumFreely available from IEEE.pp. iii
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Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 1
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Cognitive self-adaptive computing and communication systems: Test, control and adaptationFull-text access may be available. Sign in or learn about subscription options.pp. 2
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Challenges for test and design for testFull-text access may be available. Sign in or learn about subscription options.pp. 3
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An SOC platform for ADC test and measurementFull-text access may be available. Sign in or learn about subscription options.pp. 4-7
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A scheme of logic self repair including local interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 8-11
Architecture model for approximate palindrome detectionFull-text access may be available. Sign in or learn about subscription options.pp. 90-95
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Comparison of different test strategies on a mixed-signal circuitFull-text access may be available. Sign in or learn about subscription options.pp. 16-19
Packet header analysis and field extraction for multigigabit networksFull-text access may be available. Sign in or learn about subscription options.pp. 96-101
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Case Study : A class E power amplifier for ISO-14443AFull-text access may be available. Sign in or learn about subscription options.pp. 20-23
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Fast congestion-aware timing-driven placement for island FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 24-27
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Analysis and optimization of ring oscillator using sub-feedback schemeFull-text access may be available. Sign in or learn about subscription options.pp. 28-29
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Improve clock gating through power-optimal enable function selectionFull-text access may be available. Sign in or learn about subscription options.pp. 30-33
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A fast untestability proof for SAT-based ATPGFull-text access may be available. Sign in or learn about subscription options.pp. 38-43
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The impact of EFSM composition on functional ATPGFull-text access may be available. Sign in or learn about subscription options.pp. 44-49
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An efficient fault simulation technique for transition faults in non-scan sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 50-55
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Self-timed full adder designs based on hybrid input encodingFull-text access may be available. Sign in or learn about subscription options.pp. 56-61
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Optimization concepts for self-healing asynchronous circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 62-67
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Asynchronous two-level logic of reduced costFull-text access may be available. Sign in or learn about subscription options.pp. 68-73
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Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 74-77
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Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSSFull-text access may be available. Sign in or learn about subscription options.pp. 78-83
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BIST assisted wideband digital compensation for MB-UWB transmittersFull-text access may be available. Sign in or learn about subscription options.pp. 84-89
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A symbolic RTL synthesis for LUT-based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 102-107
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Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testingFull-text access may be available. Sign in or learn about subscription options.pp. 108-113
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Using 3-valued memory representation for state space reduction in embedded assembly code model checkingFull-text access may be available. Sign in or learn about subscription options.pp. 114-119
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An on-line testing scheme for repairing purposes in Flash memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 120-123
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Power devices current monitoring using horizontal and vertical magnetic force sensorFull-text access may be available. Sign in or learn about subscription options.pp. 124-127
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Measurement of power supply noise tolerance of self-timed processorFull-text access may be available. Sign in or learn about subscription options.pp. 128-131
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Test scheme for switched-capacitor circuits by digital analysesFull-text access may be available. Sign in or learn about subscription options.pp. 132-135
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Structural test of programmed FPGA circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 136-139
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Low voltage precharge CMOS logicFull-text access may be available. Sign in or learn about subscription options.pp. 140-143
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MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audioFull-text access may be available. Sign in or learn about subscription options.pp. 144-147
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Effective mars rover platform design with Hardware / Software co-designFull-text access may be available. Sign in or learn about subscription options.pp. 148-151
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On the role of the power supply as an entry for common cause faultsFull-text access may be available. Sign in or learn about subscription options.pp. 152-157
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An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditionsFull-text access may be available. Sign in or learn about subscription options.pp. 158-163
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Effective BIST for crosstalk faults in interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 164-169
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MTPP - Modular Traffic Processing PlatformFull-text access may be available. Sign in or learn about subscription options.pp. 170-173
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Simulation and planning method for on-chip power distribution Full-text access may be available. Sign in or learn about subscription options.pp. 174-177
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Experience in Virtual Testing of RSD cyclic A/D convertersFull-text access may be available. Sign in or learn about subscription options.pp. 178-181
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A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 182-185
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0.5V 160-MHz 260uW all digital phase-locked loopFull-text access may be available. Sign in or learn about subscription options.pp. 186-193
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0.18 Full-text access may be available. Sign in or learn about subscription options.pp. 194-197
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Hardware solution of chaos based image encryptionFull-text access may be available. Sign in or learn about subscription options.pp. 198-201
Round-level concurrent error detection applied to Advanced Encryption StandardFull-text access may be available. Sign in or learn about subscription options.pp. 270-275
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Diagnosis of faulty units in regular graphs under the PMC modelFull-text access may be available. Sign in or learn about subscription options.pp. 202-205
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All digital baseband 50 Mbps data recovery using 5Full-text access may be available. Sign in or learn about subscription options.pp. 206-209
TTTC: Test Technology Technical CouncilFreely available from IEEE.pp. 282-284
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Contactless characterization of MEMS devices using optical microscopyFull-text access may be available. Sign in or learn about subscription options.pp. 210-213
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A comprehensive approach for soft error tolerant Four State LogicFull-text access may be available. Sign in or learn about subscription options.pp. 214-217
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High-level symbolic simulation for automatic model extractionFull-text access may be available. Sign in or learn about subscription options.pp. 218-221
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Global parametric faults identification with the use of Differential EvolutionFull-text access may be available. Sign in or learn about subscription options.pp. 222-225
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Forward and backward guarding in early output logicFull-text access may be available. Sign in or learn about subscription options.pp. 226-229
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Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 230-233
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Contention-avoiding custom topology generation for network-on-chipFull-text access may be available. Sign in or learn about subscription options.pp. 234-237
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Enhanced LEON3 core for superscalar processingFull-text access may be available. Sign in or learn about subscription options.pp. 238-241
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Ultra low-voltage switched current mirrorFull-text access may be available. Sign in or learn about subscription options.pp. 242-245
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Self-timed thermal sensing and monitoring of multicore systemsFull-text access may be available. Sign in or learn about subscription options.pp. 246-251
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A CMOS bio-impedance measurement systemFull-text access may be available. Sign in or learn about subscription options.pp. 252-257
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 258-263
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Comprehensive bridging fault diagnosis based on the SLAT paradigmFull-text access may be available. Sign in or learn about subscription options.pp. 264-269
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Author indexFreely available from IEEE.pp. 276-277
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