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1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Oct. 20 1997 to Oct. 22 1997

Paris, FRANCE

ISSN: 1063-6722

ISBN: 0-8186-8168-3

Table of Contents

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI SystemsFreely available from IEEE.pp. iii
Message from the Symposium ChairsFreely available from IEEE.pp. x
Session 1: Critical Area
Improved Yield Model for Submicron DomainFull-text access may be available. Sign in or learn about subscription options.pp. 2
by Witold A. Pleskacz, Wojciech Maly
Session 1: Critical Area
Application of a yield model merging critical areas and defectivity to industrial productsFull-text access may be available. Sign in or learn about subscription options.pp. 11
by S. Levasseur, F. Duvivier
Session 1: Critical Area
Efficient critical area estimation for arbitrary defect shapesFull-text access may be available. Sign in or learn about subscription options.pp. 20
by G.A. Allan, A.J. Walton
Session 1: Critical Area
Realistic Fault Extraction for High-Quality Design and Test of VLSI SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 29
by F.M. Goncalves, I.C. Teixeira, J.P. Teixeira
Session 1: Critical Area
Crosstalk Minimization in Three-Layer HVH Channel RoutingFull-text access may be available. Sign in or learn about subscription options.pp. 38
by Zhan Chen, Israel Koren
Session 2: Yield Management
Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and LimitsFull-text access may be available. Sign in or learn about subscription options.pp. 44
by Pascal Bichebois, Pierre Mathery
Session 2: Yield Management
An examination of empirically derived within-die local probabilities of failureFull-text access may be available. Sign in or learn about subscription options.pp. 53
by A. Gandhi, S. Hall, R. Harris
Session 2: Yield Management
Detection of Yield TrendsFull-text access may be available. Sign in or learn about subscription options.pp. 62
by Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
Session 2: Yield Management
A Statistical Approach To Identify Semiconductor Process Equipment Related Yield ProblemsFull-text access may be available. Sign in or learn about subscription options.pp. 69
by Allan Y. Wong
Session 3: Test and Test Generation
Testing of programmable logic devices (PLD) with faulty resourcesFull-text access may be available. Sign in or learn about subscription options.pp. 76
by D.G. Ashen, F.J. Meyer, N. Park, F. Lombardi
Session 3: Test and Test Generation
Configuration-Specific Test Pattern Extraction for Field Programmable Gate ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 85
by F. Ferrandi, F. Fummi, L. Pozzi, M.G. Sami
Session 3: Test and Test Generation
Concurrent testing of VLSI digital signal processors using mutation based testingFull-text access may be available. Sign in or learn about subscription options.pp. 94
by C. Aktouf, G. Al-Hayek, C. Robach
Session 3: Test and Test Generation
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter DeviationsFull-text access may be available. Sign in or learn about subscription options.pp. 100
by S.J. Spinks, C.D. Chalk, I.M. Bell, M. Zwolinski
Panel Session
Techniques for Yield ManagementFull-text access may be available. Sign in or learn about subscription options.
Session 4: Self Checking and Coding
Fast and area-time efficient Berger code checkersFull-text access may be available. Sign in or learn about subscription options.pp. 110
by Yu-Yau Guo, Jien-Chung Lo, C. Metra
Session 4: Self Checking and Coding
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codesFull-text access may be available. Sign in or learn about subscription options.pp. 119
by S.J. Piestrak
Session 4: Self Checking and Coding
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n CodesFull-text access may be available. Sign in or learn about subscription options.pp. 128
by X. Kavousianos, D. Nikolos, G. Sidiropoulos
Session 4: Self Checking and Coding
Compact and low power on-line self-testing voting schemeFull-text access may be available. Sign in or learn about subscription options.pp. 137
by C. Metra, M. Favalli, B. Ricco
Session 5: Cost Modeling
A Cost Model for VLSI / MCM SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 148
by Michel Kafrouni, Claude Thibeault, Yvon Savaria
Session 5: Cost Modeling
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost modelFull-text access may be available. Sign in or learn about subscription options.pp. 157
by Y. Gagnon, Y. Savaria, M. Meunier, C. Thibeault
Session 5: Cost Modeling
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICsFull-text access may be available. Sign in or learn about subscription options.pp. 166
by Israel Koren, Zahava Koren
Session 5: Cost Modeling
Validating fault tolerant designs using laser fault injection (LFI)Full-text access may be available. Sign in or learn about subscription options.pp. 175-183
by J.R. Samson Jr., W. Moreno, F. Falquez
Session 6: Fault Tolerance
Multiple fault detection in logic resources of FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 186
by Wei Liang Huang, F.J. Meyer, F. Lombardi
Session 6: Fault Tolerance
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance CapabilitiesFull-text access may be available. Sign in or learn about subscription options.pp. 195
by X. Wendling, H. Chauvet, L. Reveret, R. Rochet, R. Leveugle
Session 6: Fault Tolerance
Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 204
by C. Bolchini, G. Buonanno, M. Cozzini, D. Sciuto, R. Stefanelli
Session 6: Fault Tolerance
Exploiting High-Level Descriptions for Circuits Fault Tolerance AssessmentsFull-text access may be available. Sign in or learn about subscription options.pp. 212
by A. Benso, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, J. Raik, R. Ubar
Session 7: Fault Tolerance II
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 218
by I. Takanami, T. Horita
Session 7: Fault Tolerance II
Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node ColoringFull-text access may be available. Sign in or learn about subscription options.pp. 227
by Nobuo Tsuda
Session 8: Error Recovery
Low-level error recovery mechanism for self-checking sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 234
by M. Favalli, C. Metra
Session 8: Error Recovery
Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMRFull-text access may be available. Sign in or learn about subscription options.pp. 243
by W. Lynn Gallagher, Earl E. Swartzlander, Jr.
Session 8: Error Recovery
Error Identification and Data Recovery in MISR-based Data CompactionFull-text access may be available. Sign in or learn about subscription options.pp. 252
by Xiaoling Sun, Wes Tutak
Session 8: Error Recovery
Harvesting Through Array Partitioning: A Solution to Achieve Defect ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 261
by F. Distante, M. G. Sami, R. Stefanelli
Session 9: Error Detection
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoringFull-text access may be available. Sign in or learn about subscription options.pp. 272
by A. Walker, A.P. Henry, P.K. Lala
Session 9: Error Detection
An IDDQ Sensor for Concurrent Timing Error DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 281
by Christopher G. Knight, Adit D. Singh, Victor P. Nelson
Session 9: Error Detection
Designing Networks with Error Detection Properties through the Fault-Error RelationFull-text access may be available. Sign in or learn about subscription options.pp. 290
by C. Bolchini, D. Sciuto, F. Salice
Session 9: Error Detection
Semi-Concurrent Error Detection in Data PathsFull-text access may be available. Sign in or learn about subscription options.pp. 298
by Anna Antola, Vincenzo Piuri, Mariagiovanna Sami
Session 9: Error Detection
On-line error detection for finite field multipliersFull-text access may be available. Sign in or learn about subscription options.pp. 307
by M. Gossel, S. Fenn, D Taylor
Session 9: Error Detection
Author IndexFreely available from IEEE.pp. 313
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