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Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

Nov. 3 2003 to Nov. 5 2003

Boston, Massachusetts

ISSN: 1063-6722

ISBN: 0-7695-2042-1

Table of Contents

Proceedings. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI SystemsFull-text access may be available. Sign in or learn about subscription options.
Introduction
Message from the Symposium ChairsFreely available from IEEE.pp. xi
Introduction
CommitteesFreely available from IEEE.pp. xii
Session 1: Yield and Defects
Yield Analysis of Compiler-Based Arrays of Embedded SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 3
by X. Wang, M. Ottavi, F. Lombardi
Session 1: Yield and Defects
Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a ChipFull-text access may be available. Sign in or learn about subscription options.pp. 11
by Tianxu Zhao, Xuchao Duan, Yue Hao, Peijun Ma
Session 1: Yield and Defects
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale IntegrationFull-text access may be available. Sign in or learn about subscription options.pp. 18
by Meng Lu, Yvon Savaria, Bing Qiu, Jacques Taillefer
Session 1: Yield and Defects
Calibration of Open Interconnect Yield ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 26
by D. K. de Vries, P. L. C. Simon
Session 1: Yield and Defects
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 34
by T. Feng, Y.B. Kim, V. Piuri
Session 2: Optoelectronics
Level-Hybrid Optoelectronic TESH Interconnection NetworkFull-text access may be available. Sign in or learn about subscription options.pp. 45
by Vijay Jain, Glenn Chapman
Session 2: Optoelectronics
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS)Full-text access may be available. Sign in or learn about subscription options.pp. 53
by Sunjaya Djaja, Glenn H. Chapman, Desmond Y.H. Cheung, Yves Audet
Session 3: Fault Analysis, Injection & Simulation
Clock Calibration Faults and their Impact on Quality of High Performance MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 63
by C. Metra, T.M. Mak, D. Rossi
Session 3: Fault Analysis, Injection & Simulation
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 71
by M. Alderighi, F. Casini, S. D'Angelo, M. Mancini, A. Marmo, S. Pastore, G.R. Sechi
CodSim - a combined delay fault simulatorFull-text access may be available. Sign in or learn about subscription options.pp. 79-86
by Wangqi Qiu, Xiang Lu, Zhuo Li, M.H. Walker, Weiping Shi
Session 4: Test & Diagnosis
BIST Based Fault Diagnosis Using Ambiguous Test SetFull-text access may be available. Sign in or learn about subscription options.pp. 89
by Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu
Session 4: Test & Diagnosis
On the Test and Diagnosis of the Perfect ShuffleFull-text access may be available. Sign in or learn about subscription options.pp. 97
by L. Schianoand, F. Lombardi
Session 4: Test & Diagnosis
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption StandardFull-text access may be available. Sign in or learn about subscription options.pp. 105
by Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri
Session 5: Current Test & Diagnosis
3DSDM: A 3 Data-Source Diagnostic MethodFull-text access may be available. Sign in or learn about subscription options.pp. 117
by Y. Hariri, C. Thibeault
Session 5: Current Test & Diagnosis
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 124
by Marco S. Dragic, Martin Margala
Session 5: Current Test & Diagnosis
CROWNE: Current Ratio Outliers with Neighbor EstimatorFull-text access may be available. Sign in or learn about subscription options.pp. 132
by Sagar S. Sabade, D. M. H. Walker
Session 5: Current Test & Diagnosis
Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current SensorsFull-text access may be available. Sign in or learn about subscription options.pp. 140
by Abhijit Prasad, D. M. H Walker
Session 6: Test Generation & Application
ATE-Amenable Test Data Compression with No Cyclic ScanFull-text access may be available. Sign in or learn about subscription options.pp. 151
by Hamidreza Hashempour, Fabrizio Lombardi
Session 6: Test Generation & Application
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test EquipmentFull-text access may be available. Sign in or learn about subscription options.pp. 159
by Fengming Zhang, Y.J. Lee, T. Kane, L. Schiano, M. Momenzadeh, Y-B Kim, F.J. Meyer, F. Lombardi, S. Max, Phil Perkinson
Session 6: Test Generation & Application
Function-Based Dynamic Compaction and its Impact on Test Set SizesFull-text access may be available. Sign in or learn about subscription options.pp. 167
by James Wingfield, Jennifer Dworak, M. Ray Mercer
Session 6: Test Generation & Application
Constrained ATPG for Broadside Transition TestingFull-text access may be available. Sign in or learn about subscription options.pp. 175
by Xiao Liu, Michael S. Hsiao
Session 7: Scan Design & Test
Test Compaction by Using Linear-Matrix Driven Scan ChainsFull-text access may be available. Sign in or learn about subscription options.pp. 185
by Sandeep Bhatia
Session 7: Scan Design & Test
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BISTFull-text access may be available. Sign in or learn about subscription options.pp. 191
by Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy
Session 7: Scan Design & Test
Design Scan Test Strategy for Single Phase Dynamic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 199
by Ching-Hwa Cheng
Session 8: BIST
Scan-Based BIST Diagnosis Using an Embedded ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 209
by Kedarnath J. Balakrishnan, Nur A. Touba
Session 8: BIST
Hybrid BIST Using an Incrementally Guided LFSRFull-text access may be available. Sign in or learn about subscription options.pp. 217
by C.V. Krishna, Nur A. Touba
Session 8: BIST
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 225
by Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
Session 9: Error Correcting Codes
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 235
by P.K. Lala
Session 9: Error Correcting Codes
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix SymbolsFull-text access may be available. Sign in or learn about subscription options.pp. 242
by Haruhiko Kaneko, Eiji Fujiwara
Session 9: Error Correcting Codes
Quadruple Time Redundancy AddersFull-text access may be available. Sign in or learn about subscription options.pp. 250
by Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander, Jr.
Session 9: Error Correcting Codes
Error Correcting Codes for Crosstalk Effect MinimizationFull-text access may be available. Sign in or learn about subscription options.pp. 257
by D. Rossi, S. Cavallotti, C. Metra
Invited Talk
A View from the Bottom: Nanometer Technology AC Parametric Failures — Why, Where, and How to DetectFull-text access may be available. Sign in or learn about subscription options.pp. 267
by Charles Hawkins, Ali Keshavarzi, Jaume Segura
Session 10: Analogue & Mixed Signal Test
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and ImplementationFull-text access may be available. Sign in or learn about subscription options.pp. 279
by Yukiya Miura, Daisuke Kato
Session 10: Analogue & Mixed Signal Test
An Approach for Selection of Test Points for Analog Fault DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 287
by Kranthi K. Pinjala, Bruce C. Kim
Session 10: Analogue & Mixed Signal Test
BiST Model for IC RF-Transceiver Front-EndFull-text access may be available. Sign in or learn about subscription options.pp. 295
by Jerzy Dąbrowski
Session 10: Analogue & Mixed Signal Test
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 303
by John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
Session 11: Defect Tolerance and Testing
Thermal Management of High Performance MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 313
by Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi
Session 11: Defect Tolerance and Testing
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 320
by Ying Zhang, Krishnendu Chakrabarty
Session 11: Defect Tolerance and Testing
Fault Tolerant Multi-Layer Neural Networks with GA TrainingFull-text access may be available. Sign in or learn about subscription options.pp. 328
by Eiko Sugawara, Masaru Fukushi, Susumu Horiguchi
Detailed comparison of dependability analyses performed at RT and gate levelsFull-text access may be available. Sign in or learn about subscription options.pp. 336-343
by A. Ammari, R. Leveugle, M. Sonza-Reorda, M. Violante
Session 11: Defect Tolerance and Testing
Low Cost Convolutional Code Based Concurrent Error Detection in FSMsFull-text access may be available. Sign in or learn about subscription options.pp. 344
by Konstantinos Rokas, Yiorgos Makris, Dimitris Gizopoulos
Session 11: Defect Tolerance and Testing
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 352
by Shervin Sharifi, Mohammad Hosseinabadi, Pedram Riahi, Zainalabedin Navabi
Session 11: Defect Tolerance and Testing
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal SignalsFull-text access may be available. Sign in or learn about subscription options.pp. 361
by John M. Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani
Session 11: Defect Tolerance and Testing
Fault Tolerant Hopfield Associative Memory on TorusFull-text access may be available. Sign in or learn about subscription options.pp. 369
by R. A. Ayoubi, H. A. Ziade, M. A. Bayoumi
Session 11: Defect Tolerance and Testing
Efficiency of Transient Bit-Flips Detection by Software Means: A Complete StudyFull-text access may be available. Sign in or learn about subscription options.pp. 377
by B. Nicolescu, P. Peronnard, R. Velazco, Y. Savaria
Session 11: Defect Tolerance and Testing
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 385
by Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
Session 11: Defect Tolerance and Testing
Regressive Testing for System-on-Chip with Unknown-Good-YieldFull-text access may be available. Sign in or learn about subscription options.pp. 393
by N.-J. Park, B. Jin, K.M. George, N. Park, M. Choi
Session 11: Defect Tolerance and Testing
Error Detection in Signed Digit Arithmetic Circuit with Parity CheckerFull-text access may be available. Sign in or learn about subscription options.pp. 401
by G.C. Cardarilli, M. Ottavi, S. Pontarelli, M. Re, A. Salsano
Session 11: Defect Tolerance and Testing
Application-Dependent Testing of FPGA InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 409
by Mehdi Baradaran Tahoori
Session 11: Defect Tolerance and Testing
Automatic Modification of Sequential Circuits for Self-Checking ImplementationFull-text access may be available. Sign in or learn about subscription options.pp. 417
by Cecilia Metra, Stefano Di Francescantonio, Martin Omaña
Session 11: Defect Tolerance and Testing
Control Constrained Resource Partitioning for Complex SoCsFull-text access may be available. Sign in or learn about subscription options.pp. 425
by Dan Zhao, Shambhu Upadhyaya, Martin Margala
Session 11: Defect Tolerance and Testing
Partial Error Masking to Reduce Soft Error Failure Rate in Logic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 433
by Kartik Mohanram, Nur A. Touba
Session 12: FPGA & Memory Test
An Integrated Design Approach for Self-Checking FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 443
by C. Bolchini, F. Salice, D. Sciuto, R. Zavaglia
Session 12: FPGA & Memory Test
Power-Constrained Embedded Memory BIST ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 451
by Bai Hong Fang, Nicola Nicolici
Author indexFreely available from IEEE.pp. 605-607
Session 12: FPGA & Memory Test
A Memory Built-In Self-Repair for High Defect Densities Based on Error PolaritiesFull-text access may be available. Sign in or learn about subscription options.pp. 459
by M. Nicolaidis, N. Achouri, L. Anghel
Session 12: FPGA & Memory Test
Redundancy, Repair, and Test Features of a 90nm Embedded SRAM GeneratorFull-text access may be available. Sign in or learn about subscription options.pp. 467
by Rob Aitken, Neeraj Dogra, Dhrumil Gandhi, Scott Becker
Session 12: FPGA & Memory Test
An Efficient Functional Test for the Massively-Parallel C ˙RAM Logic-Enhanced Memory ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 475
by X. Sun, B. F. Cockburn, D. G. Elliott
Session 13: Design Verification & Synthesis
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 485
by Hamid R. Zarandi, Seyed Ghassem Miremadi, Alireza Ejlali
Session 13: Design Verification & Synthesis
Preliminary Validation of an Approach Dealing with Processor ObsolescenceFull-text access may be available. Sign in or learn about subscription options.pp. 493
by L. Anghel, R. Velazco, S. Saleh, S. Deswaertes, A. El Moucary
Session 14: SoC & Core Test
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA CoreFull-text access may be available. Sign in or learn about subscription options.pp. 503
by Gang Zeng, Hideo Ito
Session 14: SoC & Core Test
A Uni.ed SOC Test Approach Based on Test Data Compression and TAM DesignFull-text access may be available. Sign in or learn about subscription options.pp. 511
by Vikram Iyengar, Anshuman Chandra
Session 14: SoC & Core Test
Embedded Compact Deterministic Test for IP-Protected CoresFull-text access may be available. Sign in or learn about subscription options.pp. 519
by Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici
Session 15: System Reliability
System-Level Analysis of Fault Effects in an Automotive EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 529
by F. Corno, S. Tosato, P. Gabrielli
Dependability analysis of CAN networks: an emulation-based approachFull-text access may be available. Sign in or learn about subscription options.pp. 537-544
by J. Perez, M. Sonza Reorda, M. Violante
Session 16: Fault Tolerance
Exploiting Instruction Redundancy for Transient Fault ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 547
by Toshinori Sato
Session 16: Fault Tolerance
An Integrated Fault-Tolerant Design Framework for VLIW ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 555
by Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai
Session 16: Fault Tolerance
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check CodeFull-text access may be available. Sign in or learn about subscription options.pp. 563
by Sobeeh Almukhaizim, Yiorgos Makris
Session 16: Fault Tolerance
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area OverheadFull-text access may be available. Sign in or learn about subscription options.pp. 571
by Vinu Vijay Kumar, John Lach
Soft-error detection using control flow assertionsFull-text access may be available. Sign in or learn about subscription options.pp. 581-588
by O. Goloubeva, M. Rebaudengo, M. Sonza Reorda, M. Violante
Session 17: Soft Errors
SIED: Software Implemented Error DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 589
by B. Nicolescu, Y. Savaria, R. Velazco
Session 17: Soft Errors
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 597
by Atul Maheshwari, Israel Koren, Wayne Burleson
Author Index
nullFreely available from IEEE.pp. 605
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