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2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Oct. 7 2009 to Oct. 9 2009

Chicago, IL

Table of Contents

TTTC: Test Technology Technical CouncilFreely available from IEEE.pp. xvi-xviii
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In Memoriam: Professor Susumu HoriguchiFreely available from IEEE.pp. xiv-xv
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[Copyright notice]Freely available from IEEE.pp. iv
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Table of contentsFreely available from IEEE.pp. v-ix
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Program CommitteeFreely available from IEEE.pp. xiii
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Title Page iFreely available from IEEE.pp. i
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Title Page iiiFreely available from IEEE.pp. iii
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Message from the Symposium ChairsFreely available from IEEE.pp. x-xi
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Organizing CommitteeFreely available from IEEE.pp. xii
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The Future of Test -- Product Integration and its Impact on TestFull-text access may be available. Sign in or learn about subscription options.pp. 3
by Michael Campbell
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Low DPM: Why Do We Need it and What Does it Cost!Full-text access may be available. Sign in or learn about subscription options.pp. 7
by Sandeep P. Kumar
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Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 11-19
by George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, F. Foster Dai, Victor P. Nelson
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Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control PointsFull-text access may be available. Sign in or learn about subscription options.pp. 20-28
by Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
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Soft Core Embedded Processor Based Built-In Self-Test of FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 29-37
by Bradley F. Dutton, Charles E. Stroud
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On-chip Generation of the Second Primary Input Vectors of Broadside TestsFull-text access may be available. Sign in or learn about subscription options.pp. 38-46
by Irith Pomeranz, Sudhakar M. Reddy
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Flip-Flop Hardening and Selection for Soft Error and Delay Fault ResilienceFull-text access may be available. Sign in or learn about subscription options.pp. 49-57
by Mingjing Chen, Alex Orailoglu
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A Novel Hardened Design of a CMOS Memory Cell at 32nmFull-text access may be available. Sign in or learn about subscription options.pp. 58-64
by Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
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Novel High Speed Robust LatchFull-text access may be available. Sign in or learn about subscription options.pp. 65-73
by Martin Omaña, Daniele Rossi, Cecilia Metra
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Are Robust Circuits Really Robust?Full-text access may be available. Sign in or learn about subscription options.pp. 77
by Sybille Hellebrand, Marc Hunger
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Challenges in Delay Testing of Integrated CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 81-82
by D.M.H. Walker
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Using RRNS Codes for Cluster Faults Tolerance in Hybrid MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 85-93
by Nor Zaidi Haron, Said Hamdioui
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Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and PowerFull-text access may be available. Sign in or learn about subscription options.pp. 94-102
by Aaron Dingler, M. Jafar Siddiq, Michael Niemier, X. Sharon Hu, M. Tanvir Alam, Gary Bernstein, Wolfgang Porod
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Coded DNA Self-Assembly for Error Detection/LocationFull-text access may be available. Sign in or learn about subscription options.pp. 103-111
by Zahra Mashreghian Arani, Masoud Hashempour, Fabrizio Lombardi
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Errors in DNA Self-Assembly by Synthesized Tile SetsFull-text access may be available. Sign in or learn about subscription options.pp. 112-120
by Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi
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Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 123
by Naveed Sherwani
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Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable SensorsFull-text access may be available. Sign in or learn about subscription options.pp. 127-135
by Martin Omaña, Marcin Marzencki, Roberto Specchia, Cecilia Metra, Bozena Kaminska
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SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000Full-text access may be available. Sign in or learn about subscription options.pp. 136-144
by Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham
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Reduced Precision Checking for a Floating Point AdderFull-text access may be available. Sign in or learn about subscription options.pp. 145-152
by Patrick J. Eibl, Andrew D. Cook, Daniel J. Sorin
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Characterization of Gain Enhanced In-Field Defects in Digital ImagersFull-text access may be available. Sign in or learn about subscription options.pp. 155-163
by Jenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren
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Analysis of Resistive Open Defects in a SynchronizerFull-text access may be available. Sign in or learn about subscription options.pp. 164-172
by Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang
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A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 173-181
by Cristiana Bolchini, Fabrizio Castro, Antonio Miele
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On the Functional Qualification of a Platform ModelFull-text access may be available. Sign in or learn about subscription options.pp. 182-190
by Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe
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A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 193-201
by David Wolpert, Paul Ampadu
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A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault ToleranceFull-text access may be available. Sign in or learn about subscription options.pp. 202-210
by Yueran Gao, Haibo Wang
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Improving Memory Repair by Selective Row PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 211-219
by Muhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba
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Software-Based Hardware Fault Tolerance for Many-Core ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 223
by Hans-Joachim Wunderlich
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Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?Full-text access may be available. Sign in or learn about subscription options.pp. 224
by Marcelo Lubaszewski
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Testing of Switch Blocks in Three-Dimensional FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 227-235
by Takumi Hoshi, Kazuteru Namba, Hideo Ito
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A Study of Side-Channel Effects in Reliability-Enhancing TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 236-244
by Jianwei Dai, Lei Wang
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Reliability and Performance Analysis of FPGA-Based Fault Tolerant SystemFull-text access may be available. Sign in or learn about subscription options.pp. 245-253
by Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue
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An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 254-262
by Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis
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Minimizing Observation Points for Fault LocationFull-text access may be available. Sign in or learn about subscription options.pp. 263-267
by Snehal Udar, Dimitri Kagaris
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Optimizing Parametric BIST Using Bio-inspired Computing AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 268-276
by Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi
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Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance MechanismsFull-text access may be available. Sign in or learn about subscription options.pp. 277-285
by Meng Zhang, Anita Lungu, Daniel J. Sorin
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System Level Testing via TLM 2.0 Debug Transport InterfaceFull-text access may be available. Sign in or learn about subscription options.pp. 286-294
by Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino
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Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus FragmentsFull-text access may be available. Sign in or learn about subscription options.pp. 295-303
by Nader Alawadhi, Ozgur Sinanoglu
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Transient Error Detection and Recovery in Processor PipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 304-312
by Syed Zafar Shazli, Mehdi Baradaran Tahoori
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Fault-Tolerant Routing Algorithm for Network on Chip without Virtual ChannelsFull-text access may be available. Sign in or learn about subscription options.pp. 313-321
by Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi
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Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 322-330
by Yehua Su, Wenjing Rao
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Complementary Formal Approaches for Dependability AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 331-339
by Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud
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[Roster]Freely available from IEEE.pp. 456
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Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)Full-text access may be available. Sign in or learn about subscription options.pp. 340-348
by Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
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An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer LevelFull-text access may be available. Sign in or learn about subscription options.pp. 349-357
by Yu Liu, Kaijie Wu
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Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test SequencesFull-text access may be available. Sign in or learn about subscription options.pp. 358-366
by Irith Pomeranz, Sudhakar M. Reddy
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Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check CodesFull-text access may be available. Sign in or learn about subscription options.pp. 367-375
by Yuu Maeda, Haruhiko Kaneko
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Resilience Challenges for Exascale SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 379
by Norman Paul Jouppi
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Improving the Detectability of Resistive Open Faults in Scan CellsFull-text access may be available. Sign in or learn about subscription options.pp. 383-391
by Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz
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An Incremental Approach to Functional DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 392-400
by Luca Amati, Cristiana Bolchini, Laura Frigerio, Fabio Salice, William Eklow, Arnold Suvatne, Eugenio Brambilla, Federico Franzoso, Michele Martin
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Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 401-409
by Stelios Neophytou, Maria K. Michael, Kyriakos Christou
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Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 410-418
by Unni Chandran, Dan Zhao
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Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern MicroprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 421
by Yiorgos Makris
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A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 422
by Adit D. Singh
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Error Correction Codes for SEU and SEFI Tolerant Memory SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 425-430
by S. Pontarelli, G.C. Cardarilli, M. Re, A. Salsano
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Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 431-439
by Qiaoyan Yu, Paul Ampadu
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Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 440-448
by Bo Fu, Paul Ampadu
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Data Learning Techniques for Functional/System Fmax PredictionFull-text access may be available. Sign in or learn about subscription options.pp. 451
by Li-C. Wang
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Author IndexFreely available from IEEE.pp. 453-455
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