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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on

Apr. 21 1999 to Apr. 23 1999

Napa California

ISSN: 1082-3409

ISBN: 0-7695-0375-6

Table of Contents

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375)Freely available from IEEE.pp. i-i
Co-Chairs and Program CommitteeFreely available from IEEE.pp. x
Session 1: Tools 1, Chair: Stephen Smith
Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing SystemFull-text access may be available. Sign in or learn about subscription options.pp. 2
by Joco M.P. Cardoso, Horacio C. Neto
Session 1: Tools 1, Chair: Stephen Smith
A CAD Suite for High-Performance FPGA DesignFull-text access may be available. Sign in or learn about subscription options.pp. 12
by Brad Hutchings, Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, Mike Rytting
Session 1: Tools 1, Chair: Stephen Smith
Formal Verification of Reconfigurable CoresFull-text access may be available. Sign in or learn about subscription options.pp. 25
by Satnam Singh, Carl Johan Lillieroth
Session 2: Network Applications, Chair: Mark Shand
Transmutable Telecom System and Its ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 34
by Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Atsushi Takahara
Session 2: Network Applications, Chair: Mark Shand
Implementation and Evaluation of a Prototype Reconfigurable RouterFull-text access may be available. Sign in or learn about subscription options.pp. 44
by Jason R. Hess, David C. Lee, Scott J. Harper, Mark T. Jones, Peter M. Athanas
Session 3: Compilation, Chair: André DeHon
Pipeline Vectorization for Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 52
by Markus Weinhardt, Wayne Luk
Session 3: Compilation, Chair: André DeHon
Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory BanksFull-text access may be available. Sign in or learn about subscription options.pp. 63
by Maya B. Gokhale, Janice M. Stone
Session 3: Compilation, Chair: André DeHon
Parallelizing Applications into SiliconFull-text access may be available. Sign in or learn about subscription options.pp. 70
by Jonathan Babb, Martin Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, Saman Amarasinghe
Session 4: Architectures, Chair: Scott Hauck
Reconfigurable Elements for a Video Pipeline ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 82
by Michael R. Piacentino, Gooitzen S. vanderWal, Michael W. Hansen
Session 4: Architectures, Chair: Scott Hauck
ConCISe: A Compiler-Driven CPLD-Based Instruction Set AcceleratorFull-text access may be available. Sign in or learn about subscription options.pp. 92
by Bernardo Kastrup, Arjan Bink, Jan Hoogerbrugge
Session 5: Tools 2, Chair: Roger Woods
CPR: A Configuration Profiling ToolFull-text access may be available. Sign in or learn about subscription options.pp. 104
by Srihari Cadambi, Seth Copen Goldstein
Session 5: Tools 2, Chair: Roger Woods
Debugging Techniques for Dynamically Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 114
by Nicholas McKay, Satnam Singh
Session 5: Tools 2, Chair: Roger Woods
Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 123
by Milan Vasilko, David Cabanis
Session 6: Graphics Applications, Chair: Herman Schmit
Reconfigurable Computing for Augmented RealityFull-text access may be available. Sign in or learn about subscription options.pp. 136
by W. Luk, T.K. Lee, J.R. Rice, N. Shirazi, P.Y.K. Cheung
Session 6: Graphics Applications, Chair: Herman Schmit
Sepia: Scalable 3D Compositing Using PCI PametteFull-text access may be available. Sign in or learn about subscription options.pp. 146
by Laurent Moll, Mark Shand, Alan Heirich
Session 7: Applications, Chair: Mike Butts
An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule CheckingFull-text access may be available. Sign in or learn about subscription options.pp. 158
by Zhen Luo, Margaret Martonosi, Pranav Ashar
Session 7: Applications, Chair: Mike Butts
FAFNER-Accelerating Nesting Problems with FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 168
by J. Carlos Alves, J. Canas Ferreira, C. Albuquerque, Jose F. Oliveira, J. Soeiro Ferreira, J. Silva Matos
Session 8: DSP Applications, Chair: Phil Kuekes
Field Programmable Gate Array Based Radar Front-End Digital Signal ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 178
by Tyler J. Moeller, David R. Martinez
Session 8: DSP Applications, Chair: Phil Kuekes
Optimizing FPGA-Based Vector Product DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 188
by Dan Benyamin, John Villasenor, Wayne Luk
Session 9: Run Time Systems, Chair: Satnam Singh
PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 200
by Ronald Laufer, R. Reed Taylor, Herman Schmit
Session 9: Run Time Systems, Chair: Satnam Singh
Safe and Protected Execution for the Morph/AMRM Reconfigurable ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 209
by Andrew A. Chien, Jay H. Byun
Session 9: Run Time Systems, Chair: Satnam Singh
Implementing an API for Distributed Adaptive Computing SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 222
by Mark Jones, Luke Scharf, Jonathan Scott, Chris Twaddle, Matthew Yaconis, Kuan Yao, Peter Athanas, Brian Schott
Session 10: Arithmetic, Chair: Steve Casselman
A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 232
by Gerardo Orlando, Christof Paar
Session 10: Arithmetic, Chair: Steve Casselman
Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D WarpingFull-text access may be available. Sign in or learn about subscription options.pp. 240
by M.P. Leong, M.Y. Yeung, C.K. Yeung, C.W. Fu, P.A. Heng, P.H.W. Leong
Session 10: Arithmetic, Chair: Steve Casselman
Dynamic Precision Management for Loop Computations on Reconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 249
by Kiran Bondalapati, Viktor K. Prasanna
Poster Session 1
Accelerating Run-Time Reconfiguration on FCCMsFull-text access may be available. Sign in or learn about subscription options.pp. 260
by J-P Heron, R.F. Woods
Poster Session 1
A Virtual Hardware Handler for RTR SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 262
by R. Turner, R. Woods, S. Sezer, J. Heron
Poster Session 1
Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further ResultsFull-text access may be available. Sign in or learn about subscription options.pp. 264
by Eric K. Pauer, Paul D. Fiore, John M. Smith
Poster Session 1
Development System for FPGA-Based Digital CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 266
by V. Sklyarov, J. Fonseca, R. Monteiro, A. Oliveira, A. Melo, N. Lau, I. Skliarova, P. Neves, A. Ferrari
Poster Session 1
Design of a JTAG Based Run Time Reconfigurable SystemFull-text access may be available. Sign in or learn about subscription options.pp. 268
by Cynthia Cousineau, François Laperle, Yvon Savaria
Poster Session 1
Architectures for System-Level Applications of Adaptive ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 270
by Brian Schott, Chen Chen, Steve Crago, Joe Czarnaski, Matt French, Ivan Hom, Tam Tho, Terri Valenti
Poster Session 1
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 272
by Vinoo Srinivasan, Ranga Vemuri
Poster Session 1
Enabling Automatic Module Generation for FCCM CompilersFull-text access may be available. Sign in or learn about subscription options.pp. 274
by Andreas Koch
Poster Session 2
ICARUS: A Dynamically Reconfigurable Computer ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 278
by Michael Baxter
Poster Session 2
SONIC - A Plug-In Architecture for Video ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 280
by Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
Poster Session 2
A Reconfigurable Platform for Academic PurposesFull-text access may be available. Sign in or learn about subscription options.pp. 282
by Christof Teuscher, Jacques-Olivier Haenni, Hector Fabio Restrepo, Eduardo Sanchez, Francisco J. Gomez
Poster Session 2
VHDL Placement Directives for Parametric IP BlocksFull-text access may be available. Sign in or learn about subscription options.pp. 284
by James Hwang, Cameron Patterson, Sujoy Mitra
Poster Session 2
Runlength Compression Techniques for FPGA ConfigurationsFull-text access may be available. Sign in or learn about subscription options.pp. 286
by Scott Hauck, William D. Wilson
Poster Session 3
Accelerating an IR Automatic Target Recognition Application with FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 290
by Jack Jean, Xuejun Liang, Brian Drozd, Karen Tomko
Poster Session 3
Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 292
by Benjamin Levine, Senthil Natarajan, Chandra Tan, Danny Newport, Don Bouldin
Poster Session 3
Hybrid Data/Configuration Caching for Striped FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 294
by Deepali Deshpande, Arun K. Somani, Akhilesh Tyagi
Poster Session 3
On Reconfiguring Cache for ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 296
by Hue-Sung Kim, Arun K. Somani, Akhilesh Tyagi
Poster Session 3
Reconfigurable Pipelines in VLIW Execution UnitsFull-text access may be available. Sign in or learn about subscription options.pp. 298
by Ronald D. Williams, Brian D. Kuebert
Poster Session 3
Fast Online Placement for Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 300
by Kiarash Barzagan, Majid Sarrafzadeh
Poster Session 4
A Compact Fast Variable Key Size Elliptic Curve Cryptosystem CoprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 304
by Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman
Poster Session 4
A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 306
by Miron Abramovici, Jose T. de Sousa
Poster Session 4
Reducing Compilation Time of Zhong's FPGA-Based SAT SolverFull-text access may be available. Sign in or learn about subscription options.pp. 308
by Pak K. Chan, M.J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu
Poster Session 4
FPGA-Based Structures for On-Line FFT and DCTFull-text access may be available. Sign in or learn about subscription options.pp. 310
by Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John Villasenor
Poster Session 4
An FPGA-Based Fan Beam Image Reconstruction ModuleFull-text access may be available. Sign in or learn about subscription options.pp. 312
by Luiz Maltar, Felipe M.G. França, Vladimir C. Alves, Cláudio L. Amorim
Poster Session 4
B?zier Curve Rendering on Virtex(tm)Full-text access may be available. Sign in or learn about subscription options.pp. 314
by Donald MacVicar, Satnam Singh, Robert Slous
Poster Session 4
Author IndexFreely available from IEEE.pp. 318
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