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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on

Apr. 17 2000 to Apr. 19 2000

Napa, California

ISSN: 1082-3409

ISBN: 0-7695-0871-5

Table of Contents

Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)Freely available from IEEE.pp. iii-iii
Conference OrganizersFreely available from IEEE.pp. x
Session 1: Architecture, Chair: André DeHon
Design of a VLIW Compute Accelerator on the Transmogrifier-2Full-text access may be available. Sign in or learn about subscription options.pp. 3
by L. Louis Zhang, Qiang Wang, David M. Lewis
Session 1: Architecture, Chair: André DeHon
A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability ProblemsFull-text access may be available. Sign in or learn about subscription options.pp. 13
by Mark J. Boyd, Tracy Larrabee
Session 1: Architecture, Chair: André DeHon
Configuration Caching Management Techniques for Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 22
by Zhiyuan Li, Katherine Compton, Scott Hauck
Session 2: Compilation 1, Chair: Wayne Luk
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 39
by P. Banerjee, N. Shenoy, A. Choudhary, S. Hauck, C. Bachmann, M. Haldar, P. Joisha, A. Jones, A. Kanhare, A. Nayak, S. Periyacheri, M. Walkden, D. Zaretsky
Session 2: Compilation 1, Chair: Wayne Luk
Stream-Oriented FPGA Computing in the Streams-C High Level LanguageFull-text access may be available. Sign in or learn about subscription options.pp. 49
by Maya B. Gokhale, Janice M. Stone, Jeff Arnold, Mirek Kalinowski
Session 3: Applications 1, Chair: Philip Freiden
A Reconfigurable Computing Architecture for MicrosensorsFull-text access may be available. Sign in or learn about subscription options.pp. 59
by Stephen Scalera, Mark Falco, Brent Nelson
Session 3: Applications 1, Chair: Philip Freiden
FPGA Implementation of a Microcoded Elliptic Curve Cryptographic ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 68
by K.H. Leung, K.W. Ma, W.K. Wong, P.H.W. Leong
Session 3: Applications 1, Chair: Philip Freiden
Customizing Graphics Applications: Techniques and Programming InterfaceFull-text access may be available. Sign in or learn about subscription options.pp. 77
by Henry Styles, Wayne Luk
Session 4: Compilation 2, Chair: Scott Hauck
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing EnginesFull-text access may be available. Sign in or learn about subscription options.pp. 91
by Pedro Diniz, Joonseok Park
Session 4: Compilation 2, Chair: Scott Hauck
A C to HDL Compiler for Pipeline Processing on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 101
by Tsutomu Maruyama, Tsutomu Hoshino
Session 5: Cryptographic Applications, Chair: John McHenry
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm)Full-text access may be available. Sign in or learn about subscription options.pp. 113
by Cameron Patterson
Session 5: Cryptographic Applications, Chair: John McHenry
A Bit-Serial Implementation of the International Data Encryption Algorithm IDEAFull-text access may be available. Sign in or learn about subscription options.pp. 122
by M.P. Leong, O.Y.H. Cheung, K.H. Tsoi, P.H.W. Leong
Session 5: Cryptographic Applications, Chair: John McHenry
An Adaptive Cryptographic Engine for IPSec ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 132
by Andreas Dandalis, Viktor K. Prasanna, Jose D. P. Rolim
Session 6: Programming Tools, Chair: Brad Hutchings
Death of the RLOC?Full-text access may be available. Sign in or learn about subscription options.pp. 145
by Satnam Singh
Session 6: Programming Tools, Chair: Brad Hutchings
Automated Extraction of Run-Time Parameterizable Cores from Programmable Device ConfigurationsFull-text access may be available. Sign in or learn about subscription options.pp. 153
by Philip James-Roxby, Steven A. Guccione
Session 7: Fault Tolerance, Chair: Philip Kuekes
Dynamic Fault Tolerance in FPGAs via Partial ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 165
by John Emmert, Charles Stroud, Brandon Skaggs, Miron Abramovici
Session 7: Fault Tolerance, Chair: Philip Kuekes
An ACS Robotic Control Algorithm with Fault Tolerant CapabilitiesFull-text access may be available. Sign in or learn about subscription options.pp. 175
by Shu-Yi Yu, Nirmal Saxena, Edward J. McCluskey
Session 7: Fault Tolerance, Chair: Philip Kuekes
Tunable Fault Tolerance for Runtime Reconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 185
by Steven K. Sinha, Peter M. Kamarchik, Seth C. Goldstein
Session 8: Wireless Applications, Chair: Tom Kean
Synchronization in Software Radios-Carrier and Timing Recovery Using FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 195
by Chris Dick, Fred Harris, Michael Rice
Session 8: Wireless Applications, Chair: Tom Kean
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 205
by Ahmad Alsolaim, Janusz Starzyk, Jürgen Becker, Manfred Glesner
Session 9: Applications 2, Chair: Mike Butts
Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 217
by Benjamin Levine, R. Reed Taylor, Herman Schmit
Session 9: Applications 2, Chair: Mike Butts
Hardware-Software Codesign and Parallel Implementation of a Golomb Ruler Derivation EngineFull-text access may be available. Sign in or learn about subscription options.pp. 227
by Euripides Sotiriades, Apostolos Dollas, Peter Athanas
Session 9: Applications 2, Chair: Mike Butts
An FPGA-Based Coprocessor for the Parsing of Context-Free GrammarsFull-text access may be available. Sign in or learn about subscription options.pp. 236
by Cristian Ciressan, Eduardo Sanchez, Martin Rajman, Jean-Cedric Chappelier
Session 10: Applications 3, Chair: Don Bouldin
A Reliable LZ Data Compressor on Reconfigurable CoprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 249
by Wei-Je Huang, Nirmal Saxena, Edward J. McCluskey
Session 10: Applications 3, Chair: Don Bouldin
EVIDENCE: An FPGA-Based System for Photon EVent IDENtification and CEntroidingFull-text access may be available. Sign in or learn about subscription options.pp. 259
by Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi
Session 10: Applications 3, Chair: Don Bouldin
Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 267
by Michael J. Wirthlin, Steve Morrison, Paul Graham, Brian Bray
Poster Session 1
Configuration Relocation and Defragmentation for Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 279
by Katherine Compton, James Cooley, Stephen Knol, Scott Hauck
Poster Session 1
Mapping Algorithms for a Multi-Bit Data Path Processing Reconfigurable Chip RHWFull-text access may be available. Sign in or learn about subscription options.pp. 281
by T. Yamauchi, S. Nakaya, T. Inuo, N. Kajihara
Poster Session 1
Hardware Accelerator for Subgraph Isomorphism ProblemsFull-text access may be available. Sign in or learn about subscription options.pp. 283
by Shuichi Ichikawa, Lerdtanaseangtham Udorn, Kouji Konishi
Poster Session 1
A Reconfigurable Hardware Platform for Digital Real-Time Signal Processing in Television StudiosFull-text access may be available. Sign in or learn about subscription options.pp. 285
by K. Henriss, P. Rüffer, R. Ernst, S. Hasenzahl
Poster Session 1
Reconfigurable Array Media Processor (RAMP)Full-text access may be available. Sign in or learn about subscription options.pp. 287
by Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras Balsara, Jose Flores, John Wadley
Poster Session 1
Internet Connected FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 289
by Hamish Fallside, Michael John Sebastian Smith
Poster Session 1
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 291
by O. Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano
Poster Session 2
A Virtual Hardware System on a Dynamically Reconfigurable Logic DeviceFull-text access may be available. Sign in or learn about subscription options.pp. 295
by Y. Shibata, M. Uno, H. Amano, K. Furuta, T. Fujii, M. Motomura
Poster Session 2
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 297
by R. Maestre, M. Fernandez, R. Hermida, F.J. Kurdahi, N. Bagherzadeh, H. Singh
Poster Session 2
A Communication Scheduling Algorithm for Multi-FPGA SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 299
by Jinwoo Suh, Dong-In Kang, Stephen P. Crago
Poster Session 2
Preemptive Multitasking on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 301
by L. Levinson, R. Männer, M. Sessler, H. Simmler
Poster Session 2
BigSky-An On-Line Arithmetic Design Tool for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 303
by Aaron Schneider, Robert McIlhenny, M.D. Ercegovac
Poster Session 2
Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design MappingsFull-text access may be available. Sign in or learn about subscription options.pp. 305
by P. Graham, B. Hutchings, B. Nelson
Poster Session 2
Multiple Precision for Resource MinimizationFull-text access may be available. Sign in or learn about subscription options.pp. 307
by George A. Constantinides, Peter Y.K. Cheung, Wayne Luk
Poster Session 2
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-BloxFull-text access may be available. Sign in or learn about subscription options.pp. 309
by O. Mencer, H. Hübert, M. Morf, M. Flynn
Poster Session 3
An FPGA-Based Array Processor for an Ionospheric-Imaging RadarFull-text access may be available. Sign in or learn about subscription options.pp. 313
by Tim Tuan, Miguel Figueroa, Frank Lind, Chucai Zhou, Chris Diorio, John Sahr
Poster Session 3
Embedded Compilation for Multimedia ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 315
by N. Daw, S. Goldstein, D. Strelow
Poster Session 3
Interfacing Reconfigurable Logic with a CPUFull-text access may be available. Sign in or learn about subscription options.pp. 317
by K. Walker, M. Budiu, S. Goldstein
Poster Session 3
A Run-Time Reconfigurable Plug-In for the Winamp MP3 PlayerFull-text access may be available. Sign in or learn about subscription options.pp. 319
by Jonathan Scalera, Mark Jones
Poster Session 3
Accelerating Embedded Applications using Dynamically Reconfigurable Hardware and Evolutionary AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 321
by J. Harkin, T.M McGinnity, L.P Maguire
Poster Session 3
Implementation of a Configurable Controller for an AC Drive Control: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 323
by M. Imecs, P. Bikfalvi, S. Nedevschi, J. Vásárhelyi
Poster Session 3
Pattern Recognition and Reconstruction on an FPGA Coprocessor BoardFull-text access may be available. Sign in or learn about subscription options.pp. 325
by R. Männer, M. Sessler, H. Simmler
Poster Session 4
FCCMS and the Memory WallFull-text access may be available. Sign in or learn about subscription options.pp. 329
by S. Derrien, S. Rajopadhye
Poster Session 4
A C to Hardware/Software CompilerFull-text access may be available. Sign in or learn about subscription options.pp. 331
by Kiarash Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh
Poster Session 4
Evaluating Hardware Compilation TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 333
by Markus Weinhardt, Wayne Luk
Poster Session 4
Adapting Constant Multipliers in a Neural Network ImplementationFull-text access may be available. Sign in or learn about subscription options.pp. 335
by P. James-Roxby, B. Blodget
Poster Session 4
A Networked FPGA-Based Hardware Implementation of a Neural Network ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 337
by Héctor Fabio Restrepo, Ralph Hoffmann, Andres Perez-Uribe, Christof Teuscher, Eduardo Sanchez
Poster Session 4
Design of C++ Class Library and Bit-Serial Compiler for Variable-Precision Datapath Synthesis on Adaptive Computing SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 339
by Katsuharu Suzuki, Michael X. Wang, Zhao Fang, Wayne W.-M. Dai
Poster Session 4
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 341
by Timothy Courtney, Richard Turner, Roger Woods
Poster Session 4
Combining Serialization and Reconfiguration for Convolver DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 344
by Arran Derbyshire, Wayne Luk
Poster Session 4
Author IndexFreely available from IEEE.pp. 347
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