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Proceedings. 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

April 20 2004 to April 23 2004

Napa, CA, USA

Table of Contents

Conference organizersFreely available from IEEE.pp. x
Session 1: Architecture
Time-Critical Software Deceleration in an FCCMFull-text access may be available. Sign in or learn about subscription options.pp. 3-12
Session 1: Architecture
Design Patterns for Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 13-23
Session 1: Architecture
Virtual Memory Window for a Portable Reconfigurable Cryptography CoprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 24-33
Session 2: Tools I
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 37-46
Session 2: Tools I
PyGen: A MATLAB/Simulink Based Tool for Synthesizing Parameterized and Energy Efficient Designs Using FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 47-56
Session 3: Arithmetic I
Automated Least-Significant Bit Datapath Optimization for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 59-67
Session 3: Arithmetic I
An Arithmetic Library and Its Application to the N-body ProblemFull-text access may be available. Sign in or learn about subscription options.pp. 68-78
Session 3: Arithmetic I
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 79-88
Session 4: Communications Applications
A Dynamically-Reconfigurable, Power-Efficient Turbo DecoderFull-text access may be available. Sign in or learn about subscription options.pp. 91-100
Session 4: Communications Applications
A Flexible Hardware Encoder for Low-Density Parity-Check CodesFull-text access may be available. Sign in or learn about subscription options.pp. 101-111
Session 5: Networking I
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet SchedulersFull-text access may be available. Sign in or learn about subscription options.pp. 115-124
Session 5: Networking I
Deep Packet Filter with Dedicated Logic and Read Only MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 125-134
Session 5: Networking I
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 135-144
Session 6: Applications I
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 147-155
Session 6: Applications I
FPGA-Based Acceleration of the 3D Finite-Difference Time-Domain MethodFull-text access may be available. Sign in or learn about subscription options.pp. 156-163
Session 7: Tools II
Register Binding for FPGAs with Embedded MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 167-175
Session 7: Tools II
Defect and Fault Tolerance of Reconfigurable Molecular ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 176-185
Session 7: Tools II
Communications Scheduling for Concurrent Processes on Reconfigurable ComputersFull-text access may be available. Sign in or learn about subscription options.pp. 186-193
Session 8: Applications II
Reconfigurable Molecular Dynamics SimulatorFull-text access may be available. Sign in or learn about subscription options.pp. 197-206
Session 8: Applications II
Accelerating Seismic Migration Using FPGA-Based Coprocessor PlatformFull-text access may be available. Sign in or learn about subscription options.pp. 207-216
Session 9: Arithmetic II
Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS PerformanceFull-text access may be available. Sign in or learn about subscription options.pp. 219-228
Session 9: Arithmetic II
FPGA-Based Implementation of a Robust IEEE-754 Exponential UnitFull-text access may be available. Sign in or learn about subscription options.pp. 229-238
Session 9: Arithmetic II
Design of an On-Line IEEE Floating-Point Addition Unit for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 239-246
Session 10: Networking II
Scalable Pattern Matching for High Speed NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 249-257
Session 10: Networking II
Pre-Decoded CAMs for Efficient and High-Speed NIDS Pattern MatchingFull-text access may be available. Sign in or learn about subscription options.pp. 258-267
Posters
FPGA Acceleration of Rigid Molecule InteractionsFull-text access may be available. Sign in or learn about subscription options.pp. 300-301
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