1. Home
  2. Proceedings
  3. FCCM
  4. FCCM 2007
Default Cover Image

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

April 23 2007 to April 25 2007

Napa, CA

Table of Contents

Posters
A Configurable Processor Synthesis SystemFull-text access may be available. Sign in or learn about subscription options.pp. 331-332
by C. Gloster, W. Gay
15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines-TitleFreely available from IEEE.
15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines-CopyrightFreely available from IEEE.
15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - TOCFreely available from IEEE.
Introduction
Conference OrganizersFreely available from IEEE.pp. x
Session 1: Applications
Sampling from the Multivariate Gaussian Distribution using Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 3-12
by David B. Thomas, Wayne Luk
Session 1: Applications
A Fast FPGA-Based 2-Opt Solver for Small-Scale Euclidean Traveling Salesman ProblemFull-text access may be available. Sign in or learn about subscription options.pp. 13-22
by Ioannis Mavroidis, Ioannis Papaefstathiou, Dionisios Pnevmatikatos
Session 1: Applications
On the Acceleration of Shortest Path Calculations in Transportation NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 23-34
by Zachary K. Baker, Maya Gokhale
Session 2: Software Tools
Enhancing Relocatability of Partial Bitstreams for Run-Time ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 35-44
by Tobias Becker, Wayne Luk, Peter Y.K. Cheung
Session 2: Software Tools
A Library and Platform for FPGA Bitstream ManipulationFull-text access may be available. Sign in or learn about subscription options.pp. 45-54
by Adam Megacz
Session 3: System
A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 55-64
by Michael Butts, Anthony Mark Jones, Paul Wasson
Session 3: System
Configurable Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 65-72
by Chirstoforos Kachris, Chidamber Kulkarni
Session 3: System
A Reconfigurable Hardware Interface for a Modern Computing SystemFull-text access may be available. Sign in or learn about subscription options.pp. 73-84
by Philip Garcia, Katherine Compton
Session 4: Bioinformatics
FPGA Acceleration of Gene Rearrangement AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 85-94
by Jason D. Bakos
Session 4: Bioinformatics
FPGA-accelerated seed generation in Mercury BLASTPFull-text access may be available. Sign in or learn about subscription options.pp. 95-106
by Arpith Jacob, Joseph Lancaster, Jeremy Buhler, Roger D. Chamberlain
Session 5: Scientific Computing
Systolic Architecture for Computational Fluid Dynamics on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 107-116
by Kentaro Sano, Takanori Iizuka, Satoru Yamamoto
Session 5: Scientific Computing
FPGA-Based Multigrid Computation for Molecular Dynamics SimulationsFull-text access may be available. Sign in or learn about subscription options.pp. 117-126
by Yongfeng Gu, Martin C. Herbordt
Session 5: Scientific Computing
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 127-140
by Ron Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka
Session 6: Applications
Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 141-150
by Christos-S Bouganis, Iosifina Pournara, Peter Y.K. Cheung
Session 6: Applications
K-means Clustering for Multispectral Images Using Floating-Point DivideFull-text access may be available. Sign in or learn about subscription options.pp. 151-162
by Xiaojun Wang, Miriam Leeser
Session 7: Floating Point Arithmetic
Optimizing Logarithmic Arithmetic on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 163-172
by Haohuan Fu, Oskar Mencer, Wayne Luk
Session 7: Floating Point Arithmetic
Generating FPGA-Accelerated DFT LibrariesFull-text access may be available. Sign in or learn about subscription options.pp. 173-184
by Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, Jose M.F. Moura, Markus Puschel, Jeremy R. Johnson
Session 7: Floating Point Arithmetic
An FPGA implementation of pipelined multiplicative division with IEEE RoundingFull-text access may be available. Sign in or learn about subscription options.pp. 185-196
by Ronen Goldberg, Guy Even, Peter-M. Seidel
Session 8: Applications
Integer Factorization Based on Elliptic Curve Method: Towards Better Exploitation of Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 197-206
by Giacomo de Meulenaer, Francois Gosset, Guerric Meurice de Dormale, Jean-Jacques Quisquater
Session 8: Applications
Matched Filter Computation on FPGA, Cell and GPUFull-text access may be available. Sign in or learn about subscription options.pp. 207-218
by Zachary K. Baker, Maya B. Gokhale, Justin L. Tripp
Session 9: Software Tools II
A Data-Driven Approach for Pipelining Sequences of Data-Dependent LoopsFull-text access may be available. Sign in or learn about subscription options.pp. 219-228
by Rui Rodrigues, Joao M.P. Cardoso, Pedro C. Diniz
Session 9: Software Tools II
Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 229-238
by Nicholas Moore, Albert Conti, Miriam Leeser, Laurie Smith King
Session 9: Software Tools II
Mitrion-C Application Development on SGI Altix 350/RC100Full-text access may be available. Sign in or learn about subscription options.pp. 239-250
by Volodymyr V. Kindratenko, Robert J. Brunner, Adam D. Myers
Session 10: Optimization
Automatic On-chip Memory Minimization for Data ReuseFull-text access may be available. Sign in or learn about subscription options.pp. 251-260
by Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y.K. Cheung
Session 10: Optimization
Scientific Application Acceleration with Reconfigurable Functional UnitsFull-text access may be available. Sign in or learn about subscription options.pp. 261-274
by Kyle Rupnow, Keith Underwood, Katherine Compton
Posters
Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence AlignmentFull-text access may be available. Sign in or learn about subscription options.pp. 275-278
by Khaled Benkrid, Ying Liu, Abdsamad Benkrid
Posters
The Case for Dynamic Execution on Dynamic HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 279-280
by Charles Ross, Wim Bohm
Posters
On Solving RC5 Challenges with FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 281-282
by Guerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater
Posters
Operating System Integration and Performance of a Multi Stream Cipher Architecture for Reconfigurable System-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 283-284
by C.M. Wee, P.R. Sutton, N.W. Bergmann
Posters
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable LogicFull-text access may be available. Sign in or learn about subscription options.pp. 285-286
by Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
Posters
New Protection Mechanisms for Intellectual Property in Reconfigurable LogicFull-text access may be available. Sign in or learn about subscription options.pp. 287-288
by Tim Guneysu, Bodo Moller, Christof Paar
Posters
Establishing Chain of Trust in Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 289-290
by Thomas Eisenbarth, Tim Guneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier
Posters
Hand-based Interface for Augmented RealityFull-text access may be available. Sign in or learn about subscription options.pp. 291-292
by F. Javier Toledo-Moreo, J. Javier Martinez-Alvarez, J. Manuel Ferrandez-Vicente
Posters
Discrete-Time Cellular Neural Networks in FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 293-294
by J. Javier Martinez-Alvarez, F. Javier Toledo-Moreo, J. Manuel Ferrandez-Vicente
Posters
Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCsFull-text access may be available. Sign in or learn about subscription options.pp. 295-296
by G. Sassatelli, N. Saint-Jean, P. Benoit, L. Torres, M. Robert, Cristiane Woszezenki, Ismael Augusto Grehs, Fernando Moraes
Posters
Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 297-298
by Nazish Aslam, Mark Milward, Ioannis Nousias, Tughrul Arslan, Ahmet Erdogan
Posters
Software/Hardware Co-Scheduling for Reconfigurable Computing SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 299-300
by Proshanta Saha, Tarek El-Ghazawi
Posters
Mapping Real Time Operating System on Reconfigurable Instruction Cell Based ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 301-304
by Han Wei, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Erdogan
Posters
Abstracting Modern FCCMs To Provide a Single Interface to Architectural ResourcesFull-text access may be available. Sign in or learn about subscription options.pp. 305-308
by Graham Schelle, Dirk Grunwald
Posters
A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable LogicFull-text access may be available. Sign in or learn about subscription options.pp. 309-310
by Hiroshi Shinohara, Hideaki Monji, Masahiro Iida, Toshinori Sueyoshi
Posters
Heterogeneous Floorplanner for FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 311-312
by Love Singhal, Elaheh Bozorgzadeh
Posters
Automatic Self-Reconfiguration of System-on-Chip PeripheralsFull-text access may be available. Sign in or learn about subscription options.pp. 313-316
by Neil W. Bergmann, Yi Lu, John A. Williams
Posters
A Hybrid Memory Sub-system for Video Coding ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 317-318
by Su-Shin Ang, George Constantinides, Wayne Luk, Peter Cheung
Posters
Rapid Prototyping of Large-scale Analog Circuits With Field Programmable Analog ArrayFull-text access may be available. Sign in or learn about subscription options.pp. 319-320
by Faik Baskaya, Brian Gestner, Chris Twigg, Sung Kyu Lim, David V. Anderson, Paul Hasler
Posters
PixelStreams-based implementation of videodetectorFull-text access may be available. Sign in or learn about subscription options.pp. 321-322
by Marek Gorgon, Piotr Pawlik, Miroslaw Jablonski, Jaromir Przybylo
Posters
Design Space Exploration for the BLAST Algorithm ImplementationFull-text access may be available. Sign in or learn about subscription options.pp. 323-326
by Euripides Sotiriades, Apostolos Dollas
Posters
An Integrated Video Compression, Encryption and Information Hiding Architecture based on the SCAN Algorithm and the Stretch TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 327-330
by G. Chrysos, A. Dollas, N. Bourbakis, S. Mertoguno
Posters
Low-Cost Stereo Vision on an FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 333-334
by Chris Murphy, Daniel Lindquist, Ann Marie Rynning, Thomas Cecil, Sarah Leavitt, Mark L. Chang
Posters
Methodology and Experimental Setup for the Determination of System-level Dynamic Reconfiguration OverheadFull-text access may be available. Sign in or learn about subscription options.pp. 335-336
by Kyprianos Papadimitriou, Antonis Anyfantis, Apostolos Dollas
Posters
Quantifying Effective Memory Bandwidth of Platform FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 337-338
by Andrew G. Schmidt, Ron Sass
Posters
A Flexible Filter Processor for Fading Channel SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 339-342
by Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel
Posters
RBoot: Software Infrastructure for a Remote FPGA LaboratoryFull-text access may be available. Sign in or learn about subscription options.pp. 343-344
by Kushal Datta, Ron Sass
Posters
Jumble: A Hardware-in-the-Loop Simulation System for JHDLFull-text access may be available. Sign in or learn about subscription options.pp. 345-348
by David Castells-Rufas, Jordi Carrabina
Posters
Sparse Matrix-Vector Multiplication Design on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 349-352
by Junqing Sun, Gregory Peterson, Olaf Storaasli
Posters
Changing Output Quality for Thermal ManagementFull-text access may be available. Sign in or learn about subscription options.pp. 353-354
by Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood
Posters
Hardware/Software co-design of a key point detector on FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 355-356
by H. Djakou Chati, F. Muhlbauer, T. Braun, C. Bobda, K. Berns
Author Index
Author IndexFreely available from IEEE.pp. 357
Showing 62 out of 62