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2008 16th International Symposium on Field-Programmable Custom Computing Machines

April 14 2008 to April 15 2008

Palo Alto, CA

Table of Contents

Papers
A Memory-Efficient FPGA-based Classification EngineFull-text access may be available. Sign in or learn about subscription options.pp. 53-62
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MPLEM: An 80-processor FPGA Based Multiprocessor SystemFull-text access may be available. Sign in or learn about subscription options.pp. 273-274
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Titan-R: A Reconfigurable Hardware Implementation of a High-Speed CompressorFull-text access may be available. Sign in or learn about subscription options.pp. 216-225
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[Copyright notice]Freely available from IEEE.pp. iv
Papers
Table of contentsFreely available from IEEE.pp. v-viii
Papers
Title Page iFreely available from IEEE.pp. i
Papers
Title Page iiiFreely available from IEEE.pp. iii
Papers
FCCM 2008 Committee ListsFreely available from IEEE.pp. ix
Papers
Kiwi: Synthesis of FPGA Circuits from Parallel ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 3-12
by Satnam Singh, David J. Greaves
Papers
Hardware Scripting in GelFull-text access may be available. Sign in or learn about subscription options.pp. 13-22
by Jonathan Bachrach, Dany Qumsiyeh, Mark Tobenkin
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Performance Analysis with High-Level Languages for High-Performance Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 23-30
by John Curreri, Seth Koehler, Brian Holland, Alan D. George
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A SRAM-based Architecture for Trie-based IP Lookup Using FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 33-42
by Hoang Le, Weirong Jiang, Viktor K. Prasanna
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A Scalable High Throughput Firewall in FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 43-52
by Gajanan S. Jedhe, Arun Ramamoorthy, Kuruvilla Varghese
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The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 65-76
by Shannon Koh, Oliver Diessel
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Autonomous System on a Chip Adaptation through Partial Runtime ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 77-86
by Matthew French, Erik Anderson, Dong-In Kang
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Scheduling Intervals for Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 87-96
by Wenyin Fu, Katherine Compton
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DSPs, BRAMs and a Pinch of Logic: New Recipes for AES on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 99-108
by Saar Drimer, Tim Güneysu, Christof Paar
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High-Speed Elliptic Curve Cryptography Accelerator for Koblitz CurvesFull-text access may be available. Sign in or learn about subscription options.pp. 109-118
by Kimmo U. Järvinen, Jorma O. Skyttä
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An FPGA Implementation of Explicit-State Model CheckingFull-text access may be available. Sign in or learn about subscription options.pp. 119-126
by Mary Ellen Fuess, Miriam Leeser, Tim Leonard
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Power-Aware and Branch-Aware Word-Length OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 129-138
by William Osborne, Jose Coutinho, Wayne Luk, Oskar Mencer
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Simultaneous Retiming and Placement for Pipelined NetlistsFull-text access may be available. Sign in or learn about subscription options.pp. 139-148
by Ken Eguro, Scott Hauck
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Map-reduce as a Programming Model for Custom Computing MachinesFull-text access may be available. Sign in or learn about subscription options.pp. 149-159
by Jackson H.C. Yeung, C.C. Tsang, K.H. Tsoi, Bill S.H. Kwan, Chris C.C. Cheung, Anthony P.C. Chan, Philip H.W. Leong
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FPGA-Based Co-processor for Singular Value Array Reconciliation TomographyFull-text access may be available. Sign in or learn about subscription options.pp. 163-172
by Jack Coyne, David Cyganski, R. James Duckworth
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Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison StudyFull-text access may be available. Sign in or learn about subscription options.pp. 173-182
by Jeff Chase, Brent Nelson, John Bodily, Zhaoyi Wei, Dah-Jye Lee
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Multiobjective Optimization of FPGA-Based Medical Image RegistrationFull-text access may be available. Sign in or learn about subscription options.pp. 183-192
by Omkar Dandekar, William Plishker, Shuvra Bhattacharyya, Raj Shekhar
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Scaling Soft Processor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 195-205
by Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan
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Reconfigurable Work Farms on a Massively Parallel Processor ArrayFull-text access may be available. Sign in or learn about subscription options.pp. 206-215
by Michael Butts, Brad Budlong, Paul Wasson, Ed White
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Credit Risk Modelling using Hardware Accelerated Monte-Carlo SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 229-238
by David B. Thomas, Wayne Luk
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Sparse Matrix-Vector Multiplication on a Reconfigurable SupercomputerFull-text access may be available. Sign in or learn about subscription options.pp. 239-247
by David DuBois, Andrew DuBois, Carolyn Connor, Steve Poole
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An Efficient O(1) Priority Queue for Large FPGA-Based Discrete Event Simulations of Molecular DynamicsFull-text access may be available. Sign in or learn about subscription options.pp. 248-257
by Martin C. Herbordt, Francois Kosie, Josh Model
Papers
Analysis of a Dynamically Reconfigurable Dataflow Architecture and its Scalable Parallel Extension for Multi-FPGA PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 261-262
by Sven-Ole Voigt, Thomas Teufel
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Improving Performance of Partial Reconfiguration Using Strategy of Virtual DeletionFull-text access may be available. Sign in or learn about subscription options.pp. 263-264
by Tian Hangpei, Gao Deyuan, Wei Wu, Fan Xiaoya, Zhu Yian
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ShareStreams-V: A Virtualized QoS Packet Scheduling AcceleratorFull-text access may be available. Sign in or learn about subscription options.pp. 265-268
by Kangtao Kendall Chuang, Sudhakar Yalamanchili, Ada Gavrilovska, Karsten Schwan
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An Extensible I/O SubsystemFull-text access may be available. Sign in or learn about subscription options.pp. 269-270
by Bharat Sukhwani, Alessandro Forin, Richard Neil Pittman
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Multi-stage Pipelining MD5 Implementations on FPGA with Data ForwardingFull-text access may be available. Sign in or learn about subscription options.pp. 271-272
by Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi
Papers
An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed InterconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 275-276
by Hanyu Liu, Xiaolei Chen, Yajun Ha
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SMILE: Scientific Parallel Multiprocessing based on Low-Cost Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 277-278
by E. Castillo, C. Pedraza, J. Castillo, C. Camarero, Jos Bosque, R. Menendez, J.I. Martínez
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Reconfigurable Constraint Repetition Unit for Regular Expression MatchingFull-text access may be available. Sign in or learn about subscription options.pp. 279-280
by Miad Faezipour, Mehrdad Nourani
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Fast Multivariate Signature Generation in Hardware: The Case of RainbowFull-text access may be available. Sign in or learn about subscription options.pp. 281-282
by Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding, Harold W. Carter
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Configurable Flow Models for FPGA Particle Graphics EnginesFull-text access may be available. Sign in or learn about subscription options.pp. 283-284
by Andrew J. Wong, Warren J. Gross
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Runtime Filesystem Support for Reconfigurable FPGA Hardware Processes in BORPHFull-text access may be available. Sign in or learn about subscription options.pp. 285-286
by Hayden Kwok-Hay So, Robert Brodersen
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[Roster]Freely available from IEEE.pp. 326
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Efficient Reconfigurable On-Chip Buses for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 287-290
by Dirk Koch, Christian Haubelt, Jürgen Teich
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Investigation of Programming Models for Emerging FPGA-Based High Performance Computing SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 291-292
by Andrew W.H. House, Paul Chow
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Hardware Compilation from Machine Code with M2VFull-text access may be available. Sign in or learn about subscription options.pp. 293-295
by Karl Meier, Alessandro Forin
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An Implementation of the Conjugate Gradient Algorithm on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 296-297
by David DuBois, Andrew DuBois, Thomas Boorman, Carolyn Connor, Steve Poole
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FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 298-299
by Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass
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Reconfigurable Computing Cluster Project: Phase I BriefFull-text access may be available. Sign in or learn about subscription options.pp. 300-301
by Andrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass
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Scalable and Portable Architecture for Probability Density Function Estimation on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 302-303
by Karthik Nagarajan, Brian Holland, Clint Slatton, Alan D. George
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A Hardware Efficient Support Vector Machine Architecture for FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 304-305
by Kevin Irick, Michael DeBole, Vijaykrishnan Narayanan, Aman Gayasen
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Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 306-309
by Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig
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Matrix Computations on Heterogeneous Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 310-311
by Ling Zhuo, Qingbo Wang, Viktor K. Prasanna
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System Level Design Methodology for Hybrid Multi-Processor SoC on FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 312-313
by Jason Wu, John Williams, Neil Bergmann
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A New Powerful Scalable Generic Multi-Standard LDPC Decoder ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 314-315
by François Charot, Christophe Wolinski, Nicolas Fau, François Hamon
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An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 316-317
by Sherman Braganza, Miriam Leeser
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Facilitating Processor-Based DPR Systems for non-DPR ExpertsFull-text access may be available. Sign in or learn about subscription options.pp. 318-319
by Edward Chen, William Gruver, Dorian Sabaz, Lesley Shannon
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Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 320-321
by Carlos Morra, João Bispo, João M.P. Cardoso, Jürgen Becker
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Author IndexFreely available from IEEE.pp. 322-324
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