Default Cover Image

Proceedings 1998 Fourth International Symposium on High-Performance Computer Architecture

Jan. 31 1998 to Feb. 4 1998

Las Vegas, Nevada

ISBN: 0-8186-8323-6

Table of Contents

Message from the General ChairFreely available from IEEE.pp. viii
Message from the Program ChairFreely available from IEEE.pp. ix
Chairs and CommitteesFreely available from IEEE.pp. x
RefereesFreely available from IEEE.pp. xi
Session I-A: Multithreading: Session Chair: Josep Torrellas, University of Illinois
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic ParallelizationFull-text access may be available. Sign in or learn about subscription options.pp. 2
Session I-A: Multithreading: Session Chair: Josep Torrellas, University of Illinois
Control Speculation in Multithreaded Processors through Dynamic Loop DetectionFull-text access may be available. Sign in or learn about subscription options.pp. 14
Session I-A: Multithreading: Session Chair: Josep Torrellas, University of Illinois
Performance Study of a Concurrent Multithreaded ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 24
Session I-B: Routing and Communication Mechanisms: Session Chair: Dhabaleswar Panda, Ohio State University
The Sensitivity of Communication Mechanisms to Bandwidth and LatencyFull-text access may be available. Sign in or learn about subscription options.pp. 37
Session I-B: Routing and Communication Mechanisms: Session Chair: Dhabaleswar Panda, Ohio State University
Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM SwitchFull-text access may be available. Sign in or learn about subscription options.pp. 47
Session I-B: Routing and Communication Mechanisms: Session Chair: Dhabaleswar Panda, Ohio State University
A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 57
Session II-A: Communication Impact on Application Performance: Session Chair: Lawrence Rauchwerger, Texas A&M University
Challenging Applications on Fast NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 68
Session II-A: Communication Impact on Application Performance: Session Chair: Lawrence Rauchwerger, Texas A&M University
Architectural Implications of a Family of Irregular ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 80
Session II-A: Communication Impact on Application Performance: Session Chair: Lawrence Rauchwerger, Texas A&M University
The Architectural Costs of Streaming I/O: A Comparison of Workstations, Clusters, and SMPsFull-text access may be available. Sign in or learn about subscription options.pp. 90
Session II-B: Smp Clusters: Session Chair: Todd Mowry, Carnegie-Mellon University
The Effectiveness of SRAM Network Caches in Clustered DSMsFull-text access may be available. Sign in or learn about subscription options.pp. 103
Session II-B: Smp Clusters: Session Chair: Todd Mowry, Carnegie-Mellon University
Home-Based SVM Protocols for SMP Clusters: Design and PerformanceFull-text access may be available. Sign in or learn about subscription options.pp. 113
Session II-B: Smp Clusters: Session Chair: Todd Mowry, Carnegie-Mellon University
Fine-Grain Software Distributed Shared Memory on SMP ClustersFull-text access may be available. Sign in or learn about subscription options.pp. 125
Panel Session: The Emergence Of Workstation Clusters: Moderator : Dhabaleswar Panda, Ohio State University: Panelists: Andrew Chien, Alan Cox, Bob Horst, Steve Scott, J.P. Singh, and Craig Stunkel
Should We Continue To Build Mpps?Full-text access may be available. Sign in or learn about subscription options.pp. 138
Session III-A: Shared-Memory Multiprocessors: Session Chair: Pen Yew, University of Minnesota
PRISM: An Integrated Architecture for Scalable Shared MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 140
Session III-A: Shared-Memory Multiprocessors: Session Chair: Pen Yew, University of Minnesota
Enhancing Memory Use in Simple Coma: Multiplexed Simple ComaFull-text access may be available. Sign in or learn about subscription options.pp. 152
Session III-A: Shared-Memory Multiprocessors: Session Chair: Pen Yew, University of Minnesota
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 162
Session III-B: Speculation and Register Renaming: Session Chair: Manolis Katevenis, FORTH, Greece
Virtual-Physical RegistersFull-text access may be available. Sign in or learn about subscription options.pp. 175
Session III-B: Speculation and Register Renaming: Session Chair: Manolis Katevenis, FORTH, Greece
Supporting Highly-Speculative Execution via Adaptive Branch TreesFull-text access may be available. Sign in or learn about subscription options.pp. 185
Session III-B: Speculation and Register Renaming: Session Chair: Manolis Katevenis, FORTH, Greece
Speculative Versioning CacheFull-text access may be available. Sign in or learn about subscription options.pp. 195
Session IV-A: Network Interface Design: Session Chair: Steve Scott, Cray
The Impact of Data Transfer and Buffering Alternatives on Network Interface DesignFull-text access may be available. Sign in or learn about subscription options.pp. 207
Session IV-A: Network Interface Design: Session Chair: Steve Scott, Cray
Address Translation Mechanisms In Network InterfacesFull-text access may be available. Sign in or learn about subscription options.pp. 219
Session IV-A: Network Interface Design: Session Chair: Steve Scott, Cray
Exploiting Two-Case Delivery for Fast Protected MessagingFull-text access may be available. Sign in or learn about subscription options.pp. 231
Session IV-B: Compiler and Operating System Issues: Session Chair: Alan Cox, Rice University
Temporal-Based Procedure Reordering for Improved Instruction Cache PerformanceFull-text access may be available. Sign in or learn about subscription options.pp. 244
Session IV-B: Compiler and Operating System Issues: Session Chair: Alan Cox, Rice University
Performance Evaluation of Tiling for the Register LevelFull-text access may be available. Sign in or learn about subscription options.pp. 254
Session IV-B: Compiler and Operating System Issues: Session Chair: Alan Cox, Rice University
Treegion Scheduling for Wide Issue ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 266
Session IV-B: Compiler and Operating System Issues: Session Chair: Alan Cox, Rice University
Communication Across Fault-Containment Firewalls on the SGI OriginFull-text access may be available. Sign in or learn about subscription options.pp. 277
Session V-A: Enhancements for DSM Systems: Session Chair: J.P. Singh, Princeton University
Efficiently Adapting to Sharing Patterns in Software DSMsFull-text access may be available. Sign in or learn about subscription options.pp. 289
Session V-A: Enhancements for DSM Systems: Session Chair: J.P. Singh, Princeton University
Comparative Evaluation of Latency Tolerance Techniques for Software Distributed Shared MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 300
Session V-A: Enhancements for DSM Systems: Session Chair: J.P. Singh, Princeton University
Using Multicast and Multithreading to Reduce Communication in Software DSM SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 312
Session V-B: Processor Design and Performance Evaluation: Session Chair: Pradeep Dubey, IBM T. J. Watson Research Center
FPGA Based Custom Computing Machines for Irregular ProblemsFull-text access may be available. Sign in or learn about subscription options.pp. 324
Non-stalling counterflow architectureFull-text access may be available. Sign in or learn about subscription options.pp. 334-341
Session V-B: Processor Design and Performance Evaluation: Session Chair: Pradeep Dubey, IBM T. J. Watson Research Center
Partial Sampling with Reverse State Reconstruction: A New Technique for Branch Predictor Performance EstimationFull-text access may be available. Sign in or learn about subscription options.pp. 342
Session V-B: Processor Design and Performance Evaluation: Session Chair: Pradeep Dubey, IBM T. J. Watson Research Center
Index of AuthorsFreely available from IEEE.pp. 352
Showing 39 out of 39