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2009 IEEE 15th International Symposium on High Performance Computer Architecture

Feb. 14 2009 to Feb. 18 2009

Raleigh, NC

Table of Contents

FrontalFull-text access may be available. Sign in or learn about subscription options.
An intelligent IT infrastructure for the futureFull-text access may be available. Sign in or learn about subscription options.
by Prith Banerjee
Session 1 Best Paper nominees [breaker page]Freely available from IEEE.pp. 5-6
Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systemsFull-text access may be available. Sign in or learn about subscription options.
by Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
Voltage emergency prediction: Using signatures to reduce operating marginsFull-text access may be available. Sign in or learn about subscription options.
by Vijay Janapa Reddi, Meeta S. Gupta, Glenn Holloway, Gu-Yeon Wei, Michael D. Smith, David Brooks
A low-radix and low-diameter 3D interconnection network designFull-text access may be available. Sign in or learn about subscription options.
by Yi Xu, Yu Du, Bo Zhao, Xiuyi Zhou, Youtao Zhang, Jun Yang
Session 2A Multicore cache architecturesFreely available from IEEE.
Adaptive Spill-Receive for robust high-performance caching in CMPsFull-text access may be available. Sign in or learn about subscription options.
by Moinuddin K. Qureshi
Design and implementation of software-managed caches for multicores with local memoryFull-text access may be available. Sign in or learn about subscription options.
by Sangmin Seo, Jaejin Lee, Zehra Sura
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnectsFull-text access may be available. Sign in or learn about subscription options.
by Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
Practical off-chip meta-data for temporal memory streamingFull-text access may be available. Sign in or learn about subscription options.
by Thomas F. Wenisch, Michael Ferdman, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos
Session 2B ReliabilityFreely available from IEEE.
Soft error vulnerability aware process variation mitigationFull-text access may be available. Sign in or learn about subscription options.
by Xin Fu, Tao Li, Jose A. B. Fortes
Accurate microarchitecture-level fault modeling for studying hardware faultsFull-text access may be available. Sign in or learn about subscription options.
by Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve
Eliminating microarchitectural dependency from Architectural VulnerabilityFull-text access may be available. Sign in or learn about subscription options.
by Vilas Sridharan, David R. Kaeli
Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metricsFull-text access may be available. Sign in or learn about subscription options.
by Lide Duan, Bin Li, Lu Peng
Panel (joint with PPoPP)Full-text access may be available. Sign in or learn about subscription options.
Opportunities beyond single-core microprocessorsFull-text access may be available. Sign in or learn about subscription options.
by Mark D. Hill
Keynote II (joint with PPoPP)Full-text access may be available. Sign in or learn about subscription options.
Multi-core demands multi-interfacesFull-text access may be available. Sign in or learn about subscription options.
by Yale Patt
Session 3A on-chip networks - IFreely available from IEEE.
Elastic-buffer flow control for on-chip networksFull-text access may be available. Sign in or learn about subscription options.
by George Michelogiannakis, James Balfour, William J. Dally
Express Cube Topologies for on-Chip InterconnectsFull-text access may be available. Sign in or learn about subscription options.
by Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPsFull-text access may be available. Sign in or learn about subscription options.
by Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Vijaykrishnan Narayanan, Chita R. Das
Session 3B processor microarchitecture - IFreely available from IEEE.
Lightweight predication support for out of order processorsFull-text access may be available. Sign in or learn about subscription options.
by Mark Stephenson, Lixin Zhang, Ram Rangan
Blueshift: Designing processors for timing speculation from the ground up.Full-text access may be available. Sign in or learn about subscription options.
by Brian Greskamp, Lu Wan, Ulya R. Karpuzcu, Jeffrey J. Cook, Josep Torrellas, Deming Chen, Craig Zilles
Session 4A NUCA and 3-D stacked memory hierarchiesFreely available from IEEE.
PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor cachesFull-text access may be available. Sign in or learn about subscription options.
by Mainak Chaudhuri
A novel architecture of the 3D stacked MRAM L2 cache for CMPsFull-text access may be available. Sign in or learn about subscription options.
by Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large cachesFull-text access may be available. Sign in or learn about subscription options.pp. 250-261
by Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John Carter
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchyFull-text access may be available. Sign in or learn about subscription options.
by Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha Udipi, Rajeev Balasubramonian, Ravishankar Iyer, Srihari Makineni, Donald Newell
Session 4B Power/performance-efficient architectures and acceleratorsFreely available from IEEE.
Reconciling specialization and flexibility through compound circuitsFull-text access may be available. Sign in or learn about subscription options.
by Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier Temam
CAMP: A technique to estimate per-structure power at run-time using a few simple parametersFull-text access may be available. Sign in or learn about subscription options.
by Michael D. Powell, Arijit Biswas, Joel S. Emer, Shubhendu S. Mukherjee, Basit R. Sheikh, Shrirang Yardi
Variation-aware dynamic voltage/frequency scalingFull-text access may be available. Sign in or learn about subscription options.
by Sebastian Herbert, Diana Marculescu
Bridging the computation gap between programmable processors and hardwired acceleratorsFull-text access may be available. Sign in or learn about subscription options.
by Kevin Fan, Manjunath Kudlur, Ganesh Dasika, Scott Mahlke
Industrial perspectives panel (joint with PPoPP)Full-text access may be available. Sign in or learn about subscription options.
Industrial perspectives panelFull-text access may be available. Sign in or learn about subscription options.
by Parthasarathy Ranganathan
Session 5A Performance modeling and analysisFreely available from IEEE.
A first-order fine-grained multithreaded throughput modelFull-text access may be available. Sign in or learn about subscription options.
by Xi E. Chen, Tor M. Aamodt
Characterization of Direct Cache Access on multi-core systems and 10GbEFull-text access may be available. Sign in or learn about subscription options.
by Amit Kumar, Ram Huggahalli, Srihari Makineni
Session 5B On-chip networks - IIFreely available from IEEE.
MRR: Enabling fully adaptive multicast routing for CMP interconnection networksFull-text access may be available. Sign in or learn about subscription options.
by Pablo Abad, Valentin Puente, Jose-Angel Gregorio
Prediction router: Yet another low latency on-chip router architectureFull-text access may be available. Sign in or learn about subscription options.
by Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
Session 6A Security, verification, and validationFreely available from IEEE.
Fast complete memory consistency verificationFull-text access may be available. Sign in or learn about subscription options.
by Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan
Hardware-software integrated approaches to defend against software cache-based side channel attacksFull-text access may be available. Sign in or learn about subscription options.
by Jingfei Kong, Onur Aciicmez, Jean-Pierre Seifert, Huiyang Zhou
Dacota: Post-silicon validation of the memory subsystem in multi-core designsFull-text access may be available. Sign in or learn about subscription options.
by Andrew DeOrio, Ilya Wagner, Valeria Bertacco
Session 6B processor microarchitecture - IIFreely available from IEEE.
Criticality-based optimizations for efficient load processingFull-text access may be available. Sign in or learn about subscription options.
by Samantika Subramaniam, Anne Bracy, Hong Wang, Gabriel H. Loh
iCFP: Tolerating all-level cache misses in in-order processorsFull-text access may be available. Sign in or learn about subscription options.
by Andrew Hilton, Santosh Nagarakatte, Amir Roth
Feedback mechanisms for improving probabilistic memory prefetchingFull-text access may be available. Sign in or learn about subscription options.
by Ibrahim Hur, Calvin Lin
Keynote III (joint with PPoPP)Full-text access may be available. Sign in or learn about subscription options.
How to build programmable multi-core chipsFull-text access may be available. Sign in or learn about subscription options.
by Jack Dennis
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