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Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors

Oct. 2 1995 to Oct. 4 1995

Austin, Texas

ISSN: 1063-6404

ISBN: 0-8186-7165-3

Table of Contents

Welcome to ICCD' 95Freely available from IEEE.pp. xiv
ICCD' 95 Conference CommitteeFreely available from IEEE.pp. xv
ICCD' 95 Track Chairs and Committee MembersFreely available from IEEE.pp. xvi
Session 1.2.2: Architecture/Algorithms Plenary, Chair: Bing Sheu, University of Southern California, Los Angeles
Statistical generalization: theory and applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 4
Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin
Signal propagation in high-speed MCM circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 12
Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin
Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodelFull-text access may be available. Sign in or learn about subscription options.pp. 18
Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin
A CMOS gate array with dynamic-termination GTL I/O circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 25
Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University
Precise exception handling for a self-timed processorFull-text access may be available. Sign in or learn about subscription options.pp. 32
Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University
Implementing a STARI chipFull-text access may be available. Sign in or learn about subscription options.pp. 38
Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University
A high-performance asynchronous SCSI controllerFull-text access may be available. Sign in or learn about subscription options.pp. 44
Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University
Performance assessment of embedded Hw/Sw systemsFull-text access may be available. Sign in or learn about subscription options.pp. 52
Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University
A simulation environment for hardware-software codesignFull-text access may be available. Sign in or learn about subscription options.pp. 58
Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University
Performance estimation for real-time distributed embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 64
Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories
Verifying the performance of the PCI local bus using symbolic techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 72
Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories
Formal verification of a PowerPC microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 79
Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories
Extending VLSI design with higher-order logicFull-text access may be available. Sign in or learn about subscription options.pp. 85
Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp.
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 96
Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp.
A superscalar RISC processor with pseudo vector processing featureFull-text access may be available. Sign in or learn about subscription options.pp. 102
Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp.
The resource conflict methodology for early-stage design space exploration of superscalar RISC processorsFull-text access may be available. Sign in or learn about subscription options.pp. 110
Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University
Design of an efficient power distribution network for the UltraSPARC-I microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 118
Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University
Clock controller design in SuperSPARC II microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 124
Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University
Incas: a cycle accurate model of UltraSPARCFull-text access may be available. Sign in or learn about subscription options.pp. 130
Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola
Accurate device modeling techniques for efficient timing simulation of integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 138
Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola
Execution-time profiling for multiple-process behavioral synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 144
Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola
Emulation verification of the Motorola 68060Full-text access may be available. Sign in or learn about subscription options.pp. 150
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Testability analysis and insertion for RTL circuits based on pseudorandom BISTFull-text access may be available. Sign in or learn about subscription options.pp. 162
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Efficient testability enhancement for combinational circuitFull-text access may be available. Sign in or learn about subscription options.pp. 168
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Design for hierarchical testability of RTL circuits obtained by behavioral synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 173
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Synthesis for testability of large complexity controllersFull-text access may be available. Sign in or learn about subscription options.pp. 180
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
Multiprocessor design verification for the PowerPC 620 microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 188
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 196
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
A high performance bus and cache controller for PowerPC multiprocessing systemsFull-text access may be available. Sign in or learn about subscription options.pp. 204
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
Performance monitoring on the PowerPC 604 microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 212
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
Thermal placement for high-performance multichip modulesFull-text access may be available. Sign in or learn about subscription options.pp. 218
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
EPNR: an energy-efficient automated layout synthesis packageFull-text access may be available. Sign in or learn about subscription options.pp. 224
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
PEPPER-a timing driven early floorplannerFull-text access may be available. Sign in or learn about subscription options.pp. 230
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioningFull-text access may be available. Sign in or learn about subscription options.pp. 236
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functionsFull-text access may be available. Sign in or learn about subscription options.pp. 244
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
Implicit state minimization of non-deterministic FSMsFull-text access may be available. Sign in or learn about subscription options.pp. 250
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
Extending equivalence class computation to large FSMsFull-text access may be available. Sign in or learn about subscription options.pp. 258
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
Efficient state assignment framework for asynchronous state graphsFull-text access may be available. Sign in or learn about subscription options.pp. 692
Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin
Adaptive routing in Clos networksFull-text access may be available. Sign in or learn about subscription options.pp. 266
Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin
Rational clocking [digital systems design]Full-text access may be available. Sign in or learn about subscription options.pp. 271
Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin
A prototype router for the massively parallel computer RWC-1Full-text access may be available. Sign in or learn about subscription options.pp. 279
Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux
Distributed automatic test pattern generation with a parallel FAN algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 698
Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux
Concurrent automatic test pattern generation algorithm for combinational circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 286
Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux
Test generation for multiple state-table faults in finite-state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 292
Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments
Pollution control cachingFull-text access may be available. Sign in or learn about subscription options.pp. 300
Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments
Caching processor general registersFull-text access may be available. Sign in or learn about subscription options.pp. 307
Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments
A dynamic cache sub-block design to reduce false sharingFull-text access may be available. Sign in or learn about subscription options.pp. 313
Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin
A programmable routing controller for flexible communications in point-to-point networksFull-text access may be available. Sign in or learn about subscription options.pp. 320
Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin
POM: a processor model for image processingFull-text access may be available. Sign in or learn about subscription options.pp. 326
Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin
A case study in low-power system-level designFull-text access may be available. Sign in or learn about subscription options.pp. 332
Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer
A novel architecture for an ATM switchFull-text access may be available. Sign in or learn about subscription options.pp. 340
Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer
Designing fibre channel fabricsFull-text access may be available. Sign in or learn about subscription options.pp. 346
Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer
Architecture and design of a 40 gigabit per second ATM switchFull-text access may be available. Sign in or learn about subscription options.pp. 352
Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc.
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 360
Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc.
An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing orderingFull-text access may be available. Sign in or learn about subscription options.pp. 366
Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc.
FPGA global routing based on a new congestion metricFull-text access may be available. Sign in or learn about subscription options.pp. 372
Session 2.4.3: Asynchronous Datapaths, Chair: Erik Brunvand, University of Utah
Asynchronous 2-D discrete cosine transform core processorFull-text access may be available. Sign in or learn about subscription options.pp. 380
Session 2.4.3: Asynchronous Datapaths, Chair: Erik Brunvand, University of Utah
A self-timed redundant-binary number to binary number converter for digital arithmetic processorsFull-text access may be available. Sign in or learn about subscription options.pp. 386
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
Design and analysis of FPGA/FPIC switch modulesFull-text access may be available. Sign in or learn about subscription options.pp. 394
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
Simultaneous area and delay minimum K-LUT mapping for K-exact networksFull-text access may be available. Sign in or learn about subscription options.pp. 402
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
DART: delay and routability driven technology mapping for LUT based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 409
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
Logic synthesis for a single large look-up tableFull-text access may be available. Sign in or learn about subscription options.pp. 415
Session 3.1.1: Design & Test Plenary, Chair: Alexander Albicki, University of Rochester
Testing-what's missing? An incomplete list of challengesFull-text access may be available. Sign in or learn about subscription options.pp. 426
Session 3.1.2: CAD Plenary, Chair: Luc Claesen, IMEC
Toward integrated system design: a global perspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 428
Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG
Analysis of conditional resource sharing using a guard-based control representationFull-text access may be available. Sign in or learn about subscription options.pp. 434
Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG
Multi-dimensional interleaving for time-and-memory design optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 440
Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG
High level profiling based low power synthesis techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 446
Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard
Control unit synthesis targeting low-power processorsFull-text access may be available. Sign in or learn about subscription options.pp. 454
Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard
Low power data format converter design using semi-static register allocationFull-text access may be available. Sign in or learn about subscription options.pp. 460
Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard
A 13.3ns double-precision floating-point ALU and multiplierFull-text access may be available. Sign in or learn about subscription options.pp. 466
Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida
A floating point radix 2 shared division/square root chipFull-text access may be available. Sign in or learn about subscription options.pp. 472
Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida
High-radix SRT division with speculation of quotient digitsFull-text access may be available. Sign in or learn about subscription options.pp. 479
Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida
A coprocessor for accurate and reliable numerical computationsFull-text access may be available. Sign in or learn about subscription options.pp. 686
Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University
Special purpose FPGA for high-speed digital telecommunication systemsFull-text access may be available. Sign in or learn about subscription options.pp. 486
Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University
VLSI design of densely-connected array processorsFull-text access may be available. Sign in or learn about subscription options.pp. 492
Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University
VLSI issues in memory-system design for video signal processorsFull-text access may be available. Sign in or learn about subscription options.pp. 498
Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center
Write buffer design for cache-coherent shared-memory multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 506
Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center
Reducing data access penalty using intelligent opcode-driven cache prefetchingFull-text access may be available. Sign in or learn about subscription options.pp. 512
Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center
Interrupt-based hardware support for profiling memory system performanceFull-text access may be available. Sign in or learn about subscription options.pp. 518
Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc.
Verification of a subtractive radix-2 square root algorithm and implementationFull-text access may be available. Sign in or learn about subscription options.pp. 526
Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc.
Automatic extraction of the control flow machine and application to evaluating coverage of verification vectorsFull-text access may be available. Sign in or learn about subscription options.pp. 532
Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc.
Theorem proving: not an esoteric diversion, but the unifying framework for industrial verificationFull-text access may be available. Sign in or learn about subscription options.pp. 538
Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories
An empirical study of datapath, memory hierarchy, and network in SIMD array architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 546
Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories
Memory organization for video algorithms on programmable signal processorsFull-text access may be available. Sign in or learn about subscription options.pp. 552
Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories
SSM-MP: more scalability in shared-memory multi-processorFull-text access may be available. Sign in or learn about subscription options.pp. 558
Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University
Low power and high speed multiplication design through mixed number representationsFull-text access may be available. Sign in or learn about subscription options.pp. 566
Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University
Minimal self-correcting shift countersFull-text access may be available. Sign in or learn about subscription options.pp. 571
Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University
Estimation of sequential circuit activity considering spatial and temporal correlationsFull-text access may be available. Sign in or learn about subscription options.pp. 577
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
A symbolic-simulation approach to the timing verification of interacting FSMsFull-text access may be available. Sign in or learn about subscription options.pp. 584
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
Incremental methods for FSM traversalFull-text access may be available. Sign in or learn about subscription options.pp. 590
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
Extraction of finite state machines from transistor netlists by symbolic simulationFull-text access may be available. Sign in or learn about subscription options.pp. 596
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
Dynamic minimization of OKFDDsFull-text access may be available. Sign in or learn about subscription options.pp. 602
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC
Data parallel fault simulationFull-text access may be available. Sign in or learn about subscription options.pp. 610
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC
A parallel algorithm for fault simulation based on PROOFSFull-text access may be available. Sign in or learn about subscription options.pp. 616
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC
Statistics on concurrent fault and design error simulationFull-text access may be available. Sign in or learn about subscription options.pp. 622
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC
A new architectural-level fault simulation using propagation prediction of grouped fault-effectsFull-text access may be available. Sign in or learn about subscription options.pp. 628
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