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Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors
Oct. 2 1995 to Oct. 4 1995
Austin, Texas
ISSN: 1063-6404
ISBN: 0-8186-7165-3
Table of Contents
Session 1.2.2: Architecture/Algorithms Plenary, Chair: Bing Sheu, University of Southern California, Los Angeles
Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin
Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin
Session 1.3.2: System Level Interconnect, Chair: Larry Pileggi, University of Texas at Austin
Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University
Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University
Session 1.3.3: Asynchronous Systems, Chair: Steve Nowick, Columbia University
Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University
Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University
Session 1.3.4: Embedded System Analysis, Chair: Sharon Hu, Western Michigan University
Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories
Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories
Session 1.4.1: Formal Verification Meets the Real World, Chairs: Mirian Leeser, Cornell University and P.A. Subrahmayam, AT&T Bell Laboratories
Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp.
Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp.
Session 1.4.2: Issues in Superscalar Processors, Chair: Bob Colwell, Intel Corp.
Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University
Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University
Session 1.4.3: SPARC Design Methodologies, Chair: Chin-Long Wey, Michigan State University
Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola
Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola
Session 1.4.4: Simulation, Chair: Derek Beatty, Motorola
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Session 2.2.1: Design for Testability, Chair: Sumit Dasgupta, Sematech/IBM Corp.
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
Session 2.2.2: PowerPC(tm), Chair: Tim Brodnax, IBM Corp. and Nasr Ullah, Motorola
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
Session 2.2.3: Floor Planning & Placement, Chair: Carl Sechen, University of Washington
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
Session 2.2.4: Combinational and Sequential Logic Optimization, Chair: Masahiro Fujita, Fujitsu Labs of America
Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin
Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin
Session 2.3.1: Massively Parallel Processing Interconnects, Chair: Joydeep Ghosh, University of Texas at Austin
Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux
Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux
Session 2.3.2: Test Pattern Generation, Chair: R. Molyneaux
Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments
Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments
Session 2.3.3: Caching Strategies, Chair: Jim Bondi, Texas Instruments
Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin
Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin
Session 2.3.4: Embedded System Architecture & Case Studies, Chair: Jim Browne, University of Texas at Austin
Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer
Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer
Session 2.4.1: ATM and High-Speed Networking Alternatives, Chair: Bob Horst, Tandem Computer
Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc.
Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc.
Session 2.4.2: Routing & Extraction, Chair: Lukas van Ginneken, Synopsys, Inc.
Session 2.4.3: Asynchronous Datapaths, Chair: Erik Brunvand, University of Utah
Session 2.4.3: Asynchronous Datapaths, Chair: Erik Brunvand, University of Utah
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
Session 2.4.4: FPGA - Synthesis, Chair: Steve Trimberger, Xilinx
Session 3.1.1: Design & Test Plenary, Chair: Alexander Albicki, University of Rochester
Session 3.1.2: CAD Plenary, Chair: Luc Claesen, IMEC
Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG
Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG
Session 3.2.1: Topics in High-Level Synthesis, Chair: Ahmed Jerraya, TIMA/INPG
Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard
Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard
Session 3.2.2: Low Power and High-Performance Circuits, Chair: Kit Cham, Hewlett-Packard
Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida
Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida
Session 3.2.3: Arithmetic Modules, Chair: N. Ranganathan, University of South Florida
Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University
Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University
Session 3.2.4: Architectures for Signal Processors, Chair: Kaushik Roy, Purdue University
Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center
Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center
Session 3.3.1: Memory System Performance, Chair: Pradip Bose, IBM T.J. Watson Research Center
Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc.
Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc.
Session 3.3.2: Emerging Technologies for Processor Verification, Chair: Warren Hunt, Computational Logic, Inc.
Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories
Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories
Session 3.3.3: Memory Architectures for Signal Processing, Chair: Bryan Ackland, AT&T Bell Laboratories
Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University
Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University
Session 3.3.4: Novel Design Concepts, Chair: Christos Papachristou, Case Western Reserve University
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
Session 3.4.1: FSM Verification, Chair: Gabriel Bischoff, Digital Equipment Corporation
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC
Session 3.4.2: Fault Simulation, Chair: Srimat Chakradhar, NEC