Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001
Sept. 23 2001 to Sept. 26 2001
Austin, TX, USA
Table of Contents
Keynote Addresses
Session 1.1: Asynchronous Techniques
Session 1.1: Asynchronous Techniques
Session 1.1: Asynchronous Techniques
Session 1.2: Embedded Tutorial
Session 1.3: Architectural Modeling: Performance and Power Analysis
Session 1.3: Architectural Modeling: Performance and Power Analysis
Session 1.3: Architectural Modeling: Performance and Power Analysis
Session 2.1: Caching
Session 2.1: Caching
Session 2.2: Simulation Based Verification
Session 2.2: Simulation Based Verification
Session 2.2: Simulation Based Verification
Session 2.3: Modeling of Capacitance and Crosstalk Noise
Session 2.3: Modeling of Capacitance and Crosstalk Noise
Session 2.3: Modeling of Capacitance and Crosstalk Noise
Session 3.1: Improving the Performance of Caching Structures
Session 3.1: Improving the Performance of Caching Structures
Session 3.1: Improving the Performance of Caching Structures
Session 3.2: Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
Session 3.2: Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
Session 3.2: Test Pattern Generation, Test Compaction, and Test Point Insertion for Synchronous Sequential Circuits
Session 3.3: Invited Session: Power 4 Microprocessor- Organizer: J. M. Tendler
Session 4.2: Computer Arithmetic
Session 4.2: Computer Arithmetic
Session 4.3: Circuit Sizing and Optimization
Session 4.3: Circuit Sizing and Optimization
Session 5.1: Clocking and Time-Domain Measurements
Session 5.1: Clocking and Time-Domain Measurements
Session 5.1: Clocking and Time-Domain Measurements
Session 5.1: Clocking and Time-Domain Measurements
Session 5.2: Processor Microarchitecture
Session 5.2: Processor Microarchitecture
Session 5.2: Processor Microarchitecture
Session 5.2: Processor Microarchitecture
Session 5.3: Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics
Session 5.3: Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics
Session 5.3: Invited Session: Taming Tons of Gigabytes: Innovations in Disk Drive Electronics
Session 6.1: Energy Efficiency Caches and Multiport Cache Structures
Session 6.1: Energy Efficiency Caches and Multiport Cache Structures
Session 6.2: Control by Simulation and On-line Checking
Session 6.2: Control by Simulation and On-line Checking
Session 6.2: Control by Simulation and On-line Checking
Session 6.3: CAD Algorithms for Physical Design
Session 6.3: CAD Algorithms for Physical Design
Session 6.3: CAD Algorithms for Physical Design
Session 7.1: Invited Session: Network Processors
Session 7.1: Invited Session: Network Processors
Session 7.1: Invited Session: Network Processors
Session 7.2: Formal Methods for Property Verification and Equivalence Verification
Session 7.2: Formal Methods for Property Verification and Equivalence Verification
Session 7.2: Formal Methods for Property Verification and Equivalence Verification
Session 7.3: Hardware Representation
Session 7.3: Hardware Representation
Session 8.1: Circuit Techniques
Session 8.1: Circuit Techniques
Session 8.1: Circuit Techniques
Session 8.2: DSP/Multimedia
Session 8.3: Novel Architectures and ISA Extensions
Session 8.3: Novel Architectures and ISA Extensions
Session 8.3: Novel Architectures and ISA Extensions
Session 8.3: Novel Architectures and ISA Extensions
Poster Papers
Poster Papers