ISQED 2003: 4th International Symposium on Quality Electronic Design
March 24 2003 to March 26 2003
San Jose, CA, USA
Table of Contents
Tutorial Track B: Design for Manufacturing and Yield
Tutorial Track C: IC and Package Co-Design
Tutorial Track D: Design for Reliability
Tutorial Track D: Design for Reliability
Tutorial Track D: Design for Reliability
Session 1A: Reliability and Design in Deep Submicron Technologies
Session 1A: Reliability and Design in Deep Submicron Technologies
Session 1A: Reliability and Design in Deep Submicron Technologies
Session 1B: Reducing Leakage Currents in VLSI Circuits
Session 1B: Reducing Leakage Currents in VLSI Circuits
Session 1B: Reducing Leakage Currents in VLSI Circuits
Session 1C: SoC Methodology
Session 1C: SoC Methodology
Session 2A: Testing of SoCs
Session 2A: Testing of SoCs
Session 2A: Testing of SoCs
Session 2B: Design for Manufacturability and Quality
Session 2B: Design for Manufacturability and Quality
Session 2B: Design for Manufacturability and Quality
Session 2B: Design for Manufacturability and Quality
Session 2B: Design for Manufacturability and Quality
Session 2C: Invited Papers Session-Design Considerations in Advanced Technology
Session 2C: Invited Papers Session-Design Considerations in Advanced Technology
Session 2C: Invited Papers Session-Design Considerations in Advanced Technology
Session 3A: Interconnect and Substrate Noise
Session 3A: Interconnect and Substrate Noise
Session 3A: Interconnect and Substrate Noise
Session 3A: Interconnect and Substrate Noise
Session 3B: Impact of New Standards for Design Data Modeling and Manufacturing Interface
Session 3B: Impact of New Standards for Design Data Modeling and Manufacturing Interface
Session 3B: Impact of New Standards for Design Data Modeling and Manufacturing Interface
Session 3C: Package-Design Interface Challenges
Session 3C: Package-Design Interface Challenges
Session 3C: Package-Design Interface Challenges
Evening Panel Discussion: IC and Package Co-Design: Challenge or Dream?
Plenary Session II
Session 4A: Power Analysis and Low Power Design
Session 4A: Power Analysis and Low Power Design
Session 4A: Power Analysis and Low Power Design
Session 4A: Power Analysis and Low Power Design
Session 4B: Topics in Device and Interconnect Modeling
Session 4B: Topics in Device and Interconnect Modeling
Session 4B: Topics in Device and Interconnect Modeling
Session 4C: Techniques for High-Speed Circuits and Module Generation
Session 4C: Techniques for High-Speed Circuits and Module Generation
Session 4C: Techniques for High-Speed Circuits and Module Generation
Session 5A: Timing and Noise Issues in Physical Design
Session 5A: Timing and Noise Issues in Physical Design
Session 5A: Timing and Noise Issues in Physical Design
Session 5A: Timing and Noise Issues in Physical Design
Session 5A: Timing and Noise Issues in Physical Design
Session 5B: Reliabililty Analysis
Session 5B: Reliabililty Analysis
Session 5C: Panel Discussion: Hidden Quality, Crouching Customer-How Much Does the Quality of EDA Tools Impact Electronic Design?
Session 6A: Interconnect Parasitic Effects
Session 6A: Interconnect Parasitic Effects
Session 6A: Interconnect Parasitic Effects
Session 6A: Interconnect Parasitic Effects
Session 6B: Design and Measurement Issues in Testing
Session 6B: Design and Measurement Issues in Testing
Session 6B: Design and Measurement Issues in Testing
Session 6B: Design and Measurement Issues in Testing
Session 6B: Design and Measurement Issues in Testing