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Quality Electronic Design, International Symposium on

Mar. 16 2009 to Mar. 18 2009

San Jose, CA, USA

ISBN: 978-1-4244-2952-3

Table of Contents

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Title pageFreely available from IEEE.pp. i
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CopyrightFreely available from IEEE.pp. ii
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Welcome to ISQED'09Freely available from IEEE.pp. iii
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Best papersFreely available from IEEE.pp. iv
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Quality awardFreely available from IEEE.pp. v
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Quality awardFreely available from IEEE.pp. vi
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Organizing committeeFreely available from IEEE.pp. vii-xiii
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ISQED 2009 conference at a glanceFreely available from IEEE.pp. xiv
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Table of contentFreely available from IEEE.pp. xv-xxiv
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Small embeddable NBTI sensors (SENS) for tracking on-chip performance decayFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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NBTI-aware statistical circuit delay assessmentFull-text access may be available. Sign in or learn about subscription options.pp. 13-18
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On the efficacy of input Vector Control to mitigate NBTI effects and leakage powerFull-text access may be available. Sign in or learn about subscription options.pp. 19-26
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On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designsFull-text access may be available. Sign in or learn about subscription options.pp. 33-39
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Worst case timing jitter and amplitude noise in differential signalingFull-text access may be available. Sign in or learn about subscription options.pp. 40-46
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A PVT aware accurate statistical logic library for high-Full-text access may be available. Sign in or learn about subscription options.pp. 47-54
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Leakage optimization using transistor-level dual threshold voltage cell libraryFull-text access may be available. Sign in or learn about subscription options.pp. 62-67
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Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distributionFull-text access may be available. Sign in or learn about subscription options.pp. 68-73
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Characterization of sequential cells for constraint sensitivitiesFull-text access may be available. Sign in or learn about subscription options.pp. 74-79
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Architecture design exploration of three-dimensional (3D) integrated DRAMFull-text access may be available. Sign in or learn about subscription options.pp. 86-90
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Accurate buffer modeling with slew propagation in subthreshold circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 91-96
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Robust differential asynchronous nanoelectronic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 97-102
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The design of a low-power high-speed current comparator in 0.35-Full-text access may be available. Sign in or learn about subscription options.pp. 107-111
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Design and application of multimodal power gating structuresFull-text access may be available. Sign in or learn about subscription options.pp. 120-126
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Revisiting the linear programming framework for leakage power vs. performance optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 127-134
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Parameter tuning in SVM-based power macro-modelingFull-text access may be available. Sign in or learn about subscription options.pp. 135-140
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Performance-energy tradeoffs in reliable NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 141-146
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3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICsFull-text access may be available. Sign in or learn about subscription options.pp. 147-155
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New subthreshold concepts in 65nm CMOS technologyFull-text access may be available. Sign in or learn about subscription options.pp. 162-166
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On-chip transistor characterization arrays with digital interfaces for variability characterizationFull-text access may be available. Sign in or learn about subscription options.pp. 167-171
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Yield evaluation of analog placement with arbitrary capacitor ratioFull-text access may be available. Sign in or learn about subscription options.pp. 179-184
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Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technologyFull-text access may be available. Sign in or learn about subscription options.pp. 185-189
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Statistical yield analysis of silicon-on-insulator embedded DRAMFull-text access may be available. Sign in or learn about subscription options.pp. 190-194
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Trading off higher execution latency for increased reliability in tile-based massive multi-core architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 201-207
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A Simulation-based strategy used in electrical design for reliabilityFull-text access may be available. Sign in or learn about subscription options.pp. 208-212
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Estimation and optimization of reliability of noisy digital circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 213-219
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Combinational logic SER estimation with the presence of re-convergenceFull-text access may be available. Sign in or learn about subscription options.pp. 220-225
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Effect of NDD dosage on hot-carrier reliability in DMOS transistorsFull-text access may be available. Sign in or learn about subscription options.pp. 226-229
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Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)Full-text access may be available. Sign in or learn about subscription options.pp. 230-235
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An effective approach to detect logic soft errors in digital circuits based on GRAALFull-text access may be available. Sign in or learn about subscription options.pp. 236-240
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An efficient approach to sip design integrationFull-text access may be available. Sign in or learn about subscription options.pp. 241-247
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A new low power test pattern generator using a variable-length ring counterFull-text access may be available. Sign in or learn about subscription options.pp. 248-252
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A case study on logic diagnosis for System-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 253-259
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Proactive management of X's in scan chains for compressionFull-text access may be available. Sign in or learn about subscription options.pp. 260-265
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A Built-in self-calibration scheme for pipelined ADCsFull-text access may be available. Sign in or learn about subscription options.pp. 266-271
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A geometric approach to register transfer level satisfiabilityFull-text access may be available. Sign in or learn about subscription options.pp. 272-275
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Efficient diagnosis algorithms for drowsy SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 276-279
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Incremental power optimization for multiple supply voltage designFull-text access may be available. Sign in or learn about subscription options.pp. 280-286
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IP protection platform based on watermarking techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 287-290
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Statistical static performance analysis of asynchronous circuits considering process variationFull-text access may be available. Sign in or learn about subscription options.pp. 291-296
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A software pipelining algorithm in high-level synthesis for FPGA architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 297-302
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Statistical decoupling capacitance allocation by efficient numerical quadrature methodFull-text access may be available. Sign in or learn about subscription options.pp. 309-316
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A novel ACO-based pattern generation for peak power estimation in VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 317-323
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Switch level optimization of digital CMOS gate networksFull-text access may be available. Sign in or learn about subscription options.pp. 324-329
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hArtes design flow for heterogeneous platformsFull-text access may be available. Sign in or learn about subscription options.pp. 330-338
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An efficient reliability evaluation approach for system-level design of embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 339-344
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A case study on system-level modeling by aspect-oriented programmingFull-text access may be available. Sign in or learn about subscription options.pp. 345-349
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Performance evaluation of wireless networks on chip architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 350-355
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Validating physical access layer of WiMAX using SystemVerilogFull-text access may be available. Sign in or learn about subscription options.pp. 356-359
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Accelerating jitter tolerance qualification for high speed serial interfacesFull-text access may be available. Sign in or learn about subscription options.pp. 360-365
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Efficient SAT-based techniques for Design of Experiments by using static variable orderingFull-text access may be available. Sign in or learn about subscription options.pp. 371-376
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Timing yield estimation of digital circuits using a control variate techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 382-387
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TuneLogic: Post-silicon tuning of dual-Vdd designsFull-text access may be available. Sign in or learn about subscription options.pp. 394-400
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A case for exploiting complex arithmetic circuits towards performance yield enhancementFull-text access may be available. Sign in or learn about subscription options.pp. 401-407
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A systematic approach to modeling and analysis of transient faults in logic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 408-413
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ESD event simulation automation using automatic extraction of the relevant portion of a full chipFull-text access may be available. Sign in or learn about subscription options.pp. 414-418
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Parametric analysis to determine accurate interconnect extraction corners for design performanceFull-text access may be available. Sign in or learn about subscription options.pp. 419-423
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Exploratory study on circuit and architecture design of very high density diode-switch phase change memoriesFull-text access may be available. Sign in or learn about subscription options.pp. 424-429
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Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolutionFull-text access may be available. Sign in or learn about subscription options.pp. 430-435
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Defect characterization in magnetic field coupled arraysFull-text access may be available. Sign in or learn about subscription options.pp. 436-441
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A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 447-450
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New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 459-464
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Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuitFull-text access may be available. Sign in or learn about subscription options.pp. 465-470
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Optimization strategies to improve statistical timingFull-text access may be available. Sign in or learn about subscription options.pp. 476-481
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Clock gating effectiveness metrics: Applications to power optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 482-487
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Buffer/flip-flop block planning for power-integrity-driven floorplanningFull-text access may be available. Sign in or learn about subscription options.pp. 488-493
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On temperature planarization effect of copper dummy fills in deep nanometer technologyFull-text access may be available. Sign in or learn about subscription options.pp. 494-499
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Fast characterization of parameterized cell libraryFull-text access may be available. Sign in or learn about subscription options.pp. 500-505
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Cell shifting aware of wirelength and overlapFull-text access may be available. Sign in or learn about subscription options.pp. 506-510
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Lagrangian relaxation based register placement for high-performance circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 511-516
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Implementation of power managed hyper transport system for transmission of HD videoFull-text access may be available. Sign in or learn about subscription options.pp. 517-521
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Power aware placement for FPGAs with dual supply voltagesFull-text access may be available. Sign in or learn about subscription options.pp. 522-526
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VLSI architectures of perceptual based video watermarking for real-time copyright protectionFull-text access may be available. Sign in or learn about subscription options.pp. 527-534
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VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL modelsFull-text access may be available. Sign in or learn about subscription options.pp. 535-540
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