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Proceedings
ISQED
ISQED 2009
Generate Citations
Quality Electronic Design, International Symposium on
Mar. 16 2009 to Mar. 18 2009
San Jose, CA, USA
ISBN: 978-1-4244-2952-3
Table of Contents
Papers
Title page
Freely available from IEEE.
pp. i
Papers
Copyright
Freely available from IEEE.
pp. ii
Papers
Welcome to ISQED'09
Freely available from IEEE.
pp. iii
Papers
Best papers
Freely available from IEEE.
pp. iv
Papers
Quality award
Freely available from IEEE.
pp. v
Papers
Quality award
Freely available from IEEE.
pp. vi
Papers
Organizing committee
Freely available from IEEE.
pp. vii-xiii
Papers
ISQED 2009 conference at a glance
Freely available from IEEE.
pp. xiv
Papers
Table of content
Freely available from IEEE.
pp. xv-xxiv
Papers
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay
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pp. 1-6
by
Adam C. Cabe
,
Zhenyu Qi
,
Stuart N. Wooters
,
Travis N. Blalock
,
Mircea R. Stan
Papers
A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability
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pp. 7-12
by
Chenyue Ma
,
Bo Li
,
Lining Zhang
,
Jin He
,
Xing Zhang
,
Xinnan Lin
,
Mansun Chan
Papers
NBTI-aware statistical circuit delay assessment
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pp. 13-18
by
Balaji Vaidyanathan
,
Anthony S. Oates
,
Yuan Xie
,
Yu Wang
Papers
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power
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pp. 19-26
by
Yu Wang
,
Xiaoming Chen
,
Wenping Wang
,
Varsha Balakrishnan
,
Yu Cao
,
Yuan Xie
,
Huazhong Yang
Papers
Power&variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design
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pp. 27-32
by
R. Venkatraman
,
R. Castagnetti
,
A. Teene
,
B. Mbouombouo
,
S. Ramesh
Papers
On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs
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pp. 33-39
by
Hariharan Sankaran
,
Srinivas Katkoori
Papers
Worst case timing jitter and amplitude noise in differential signaling
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pp. 40-46
by
Wei Yao
,
Yiyu Shi
,
Lei He
,
Sudhakar Pamarti
,
Yu Hu
Papers
A PVT aware accurate statistical logic library for high-
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pp. 47-54
by
Dhruva Ghai
,
Saraju P. Mohanty
,
Elias Kougianos
,
Priyadarsan Patra
Papers
A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysis
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pp. 55-61
by
Xin Wang
,
Alireza Kasnavi
,
Harold Levy
Papers
Leakage optimization using transistor-level dual threshold voltage cell library
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pp. 62-67
by
Chandra S. Nagarajan
,
Lin Yuan
,
Gang Qu
,
Barbara G. Stamps
Papers
Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution
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pp. 68-73
by
Chun-Yu Chuang
,
Wai-Kei Mak
Papers
Characterization of sequential cells for constraint sensitivities
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pp. 74-79
by
Savithri Sundareswaran
,
Rajendran Panda
,
Jacob A. Abraham
,
Yun Zhang
,
Amit Mittal
Papers
PETE: A device/circuit analysis framework for evaluation and comparison of charge based emerging devices
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pp. 80-85
by
Charles Augustine
,
Arijit Raychowdhury
,
Yunfei Gao
,
Mark Lundstrom
,
Kaushik Roy
Papers
Architecture design exploration of three-dimensional (3D) integrated DRAM
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pp. 86-90
by
Rakesh Anigundi
,
Hongbin Sun
,
Jian-Qiang Lu
,
Ken Rose
,
Tong Zhang
Papers
Accurate buffer modeling with slew propagation in subthreshold circuits
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pp. 91-96
by
Jeremy R. Tolbert
,
Saibal Mukhopadhyay
Papers
Robust differential asynchronous nanoelectronic circuits
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pp. 97-102
by
Bao Liu
Papers
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process
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pp. 103-106
by
Karthik Rajagopal
,
Aatmesh
,
Vinod Menezes
Papers
The design of a low-power high-speed current comparator in 0.35-
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pp. 107-111
by
Soheil Ziabakhsh
,
Hosein Alavi-Rad
,
Mohammad Alavi-Rad
,
Mohammad Mortazavi
Papers
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes
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pp. 112-115
by
Wai Leng Cheong
,
Brian Owens
,
Hui En Pham
,
Christopher Hanken
,
Jim Le
,
Terri Fiez
,
Kartikeya Mayaram
Papers
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition
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pp. 116-119
by
Charbel J. Akl
,
Rafic A. Ayoubi
,
Magdy A. Bayoumi
Papers
Design and application of multimodal power gating structures
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pp. 120-126
by
Ehsan Pakbaznia
,
Massoud Pedram
Papers
Revisiting the linear programming framework for leakage power vs. performance optimization
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pp. 127-134
by
Kwangok Jeong
,
Andrew B. Kahng
,
Hailong Yao
Papers
Parameter tuning in SVM-based power macro-modeling
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pp. 135-140
by
Antonio Gusmao
,
L. Miguel Silveira
,
Jose Monteiro
Papers
Performance-energy tradeoffs in reliable NoCs
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pp. 141-146
by
Ying-Cherng Lan
,
Michael C. Chen
,
Wei-De. Chen
,
Sao-Jie Chen
,
Yu-Hen Hu
Papers
3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs
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pp. 147-155
by
Siddharth Garg
,
Diana Marculescu
Papers
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation
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pp. 156-161
by
Valeriy Sukharev
,
Ara Markosian
,
Armen Kteyan
,
Levon Manukyan
,
Nikolay Khachatryan
,
Jun-Ho Choy
,
Hasmik Lazaryan
,
Henrik Hovsepyan
,
Seiji Onoue
,
Takuo Kikuchi
,
Tetsuya Kamigaki
Papers
New subthreshold concepts in 65nm CMOS technology
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pp. 162-166
by
Farshad Moradi
,
Dag T. Wisland
,
Hamid Mahmoodi
,
Ali Peiravi
,
Snorre Aunet
,
Tuan Vu Cao
Papers
On-chip transistor characterization arrays with digital interfaces for variability characterization
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pp. 167-171
by
Simeon Realov
,
William McLaughlin
,
K. L. Shepard
Papers
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments
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pp. 172-178
by
Dhruva Ghai
,
Saraju P. Mohanty
,
Elias Kougianos
Papers
Yield evaluation of analog placement with arbitrary capacitor ratio
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pp. 179-184
by
Jwu-E Chen
,
Pei-Wen Luo
,
Chin-Long Wey
Papers
Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology
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pp. 185-189
by
Aditya P. Karmarkar
,
Xiaopeng Xu
,
Victor Moroz
,
Greg Rollins
,
Xiao Lin
Papers
Statistical yield analysis of silicon-on-insulator embedded DRAM
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pp. 190-194
by
R. Kanj
,
R. Joshi
,
JB Kuang
,
J. Kim
,
M. Meterelliyoz
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W. Reohr
,
S. Nassif
,
K. Nowka
Papers
Erect of regularity-enhanced layout on printability and circuit performance of standard cells
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pp. 195-200
by
Hiroki Sunagawa
,
Haruhiko Terada
,
Akira Tsuchiya
,
Kazutoshi Kobayashi
,
Hidetoshi Onodera
Papers
Trading off higher execution latency for increased reliability in tile-based massive multi-core architectures
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pp. 201-207
by
Enric Musoll
Papers
A Simulation-based strategy used in electrical design for reliability
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pp. 208-212
by
Yan Liu
,
Scott Hareland
,
Donald Hall
,
Bill Wold
,
Roger Hubing
,
Robert Mehregan
,
Ronen Malka
,
Manish Sharma
,
Tom Lane
Papers
Estimation and optimization of reliability of noisy digital circuits
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pp. 213-219
by
Satish Sivaswamy
,
Kia Bazargan
,
Marc Riedel
Papers
Combinational logic SER estimation with the presence of re-convergence
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pp. 220-225
by
Biwei Liu
,
Shuming Chen
,
Yi Xu
Papers
Effect of NDD dosage on hot-carrier reliability in DMOS transistors
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pp. 226-229
by
Jone F. Chen
,
Kuen-Shiuan Tian
,
Shiang-Yu Chen
,
Kuo-Ming Wu
,
C. M. Liu
Papers
Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC)
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pp. 230-235
by
Amir Khatib Zadeh
,
Catherine Gebotys
Papers
An effective approach to detect logic soft errors in digital circuits based on GRAAL
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pp. 236-240
by
Hai Yu
,
Michael Nicolaidis
,
Lorena Anghel
Papers
An efficient approach to sip design integration
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pp. 241-247
by
Meng-Syue Chan
,
Chun-Yao Wang
,
Yung-Chih Chen
Papers
A new low power test pattern generator using a variable-length ring counter
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pp. 248-252
by
Bin Zhou
,
Yi-zheng Ye
,
Zhao-lin Li
,
Xin-chun Wu
,
Rui Ke3
Papers
A case study on logic diagnosis for System-on-Chip
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pp. 253-259
by
Y. Benabboud
,
A. Bosio
,
P. Girard
,
S. Pravossoudovitch
,
A. Virazel
,
L. Bouzaida
,
I. Izaute
Papers
Proactive management of X's in scan chains for compression
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pp. 260-265
by
A. Chandra
,
Y. Kanzawa
,
R. Kapur
Papers
A Built-in self-calibration scheme for pipelined ADCs
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pp. 266-271
by
Hsiu-Ming Chang
,
Kuan-Yu Lin
,
Chin-Hsuan Chen
,
Kwang-Ting Cheng
Papers
A geometric approach to register transfer level satisfiability
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pp. 272-275
by
Hector Navarro
,
Saeid Nooshabadi
,
Juan A. Montiel-Nelson
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V. Navarro
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J. Sosa
,
Jose C. Garcia
Papers
Efficient diagnosis algorithms for drowsy SRAMs
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pp. 276-279
by
Bing-Wei Huang
,
Jin-Fu Li
Papers
Incremental power optimization for multiple supply voltage design
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pp. 280-286
by
Yuchun Ma
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Xiang Qiu
,
Xiangqing He
,
Xianlong Hong
Papers
IP protection platform based on watermarking technique
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pp. 287-290
by
Yun Du
,
Yangshuo Ding
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Yujie Chen
,
Zhiqiang Gao
Papers
Statistical static performance analysis of asynchronous circuits considering process variation
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pp. 291-296
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Mohsen Raji
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Behnam Ghavami
,
Hossein Pedram
Papers
A software pipelining algorithm in high-level synthesis for FPGA architectures
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pp. 297-302
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Lei Gao
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David Zaretsky
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Gaurav Mittal
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Dan Schonfeld
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Prith Banerjee
Papers
Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterization
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pp. 303-308
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Qian Ying Tang
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Qiang Chen
,
Niloy Chatterjee
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Vedank Tripathi
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Natarajan Nandagopalan
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Sridhar Tirumala
Papers
Statistical decoupling capacitance allocation by efficient numerical quadrature method
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pp. 309-316
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Thom Jefferson A. Eguia
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Ning Mi
,
Sheldon X.-D. Tan
Papers
A novel ACO-based pattern generation for peak power estimation in VLSI circuits
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pp. 317-323
by
Yi-Ling Liu
,
Chun-Yao Wang
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Yung-Chih Chen
,
Ya-Hsin Chang
Papers
Switch level optimization of digital CMOS gate networks
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pp. 324-329
by
Leomar S. da Rosa
,
Felipe R. Schneider
,
Renato P. Ribas
,
Andre I. Reis
Papers
hArtes design flow for heterogeneous platforms
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pp. 330-338
by
Muhammad Rashid
,
Fabrizio Ferrandi
,
Koen Bertels
Papers
An efficient reliability evaluation approach for system-level design of embedded systems
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pp. 339-344
by
Adeel Israr
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Abdulhadi Shoufan
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Sorin A. Huss
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A case study on system-level modeling by aspect-oriented programming
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pp. 345-349
by
Feng Liu
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Otmane Ait Mohamed
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Xiaoyu Song
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Qingping Tan
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Performance evaluation of wireless networks on chip architectures
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pp. 350-355
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Amlan Ganguly
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Kevin Chang
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Partha Pratim Pande
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Benjamin Belzer
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Alireza Nojeh
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Validating physical access layer of WiMAX using SystemVerilog
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pp. 356-359
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Albert Chiang
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Wei-Hua Han
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Bhanu Kapoor
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Accelerating jitter tolerance qualification for high speed serial interfaces
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pp. 360-365
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Yongquan Fan
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Zeljko Zilic
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Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences
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pp. 366-370
by
Hiroaki Yoshida
,
Masahiro Fujita
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Efficient SAT-based techniques for Design of Experiments by using static variable ordering
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pp. 371-376
by
Miroslav N. Velev
,
Ping Gao
Papers
An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs
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pp. 377-381
by
Mrinal Bose
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Prashant Naphade
,
Jay Bhadra
,
Hillel Miller
Papers
Timing yield estimation of digital circuits using a control variate technique
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pp. 382-387
by
Javid Jaffari
,
Mohab Anis
Papers
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations
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pp. 388-393
by
Koustav Bhattacharya
,
Nagarajan Ranganathan
Papers
TuneLogic: Post-silicon tuning of dual-Vdd designs
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pp. 394-400
by
Stephen Bijansky
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Sae Kyu Lee
,
Adnan Aziz
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A case for exploiting complex arithmetic circuits towards performance yield enhancement
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pp. 401-407
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Shingo Watanabe
,
Masanori Hashimoto
,
Toshinori Sato
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A systematic approach to modeling and analysis of transient faults in logic circuits
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pp. 408-413
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Natasa Miskov-Zivanov
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Diana Marculescu
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ESD event simulation automation using automatic extraction of the relevant portion of a full chip
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pp. 414-418
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Thorsten Weyl
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Dave Clarke
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Karl Rinne
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James A. Power
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Parametric analysis to determine accurate interconnect extraction corners for design performance
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pp. 419-423
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Ayhan Mutlu
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Jiayong Le
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Ruben Molina
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Mustafa Celik
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Exploratory study on circuit and architecture design of very high density diode-switch phase change memories
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pp. 424-429
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Shu Li
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Tong Zhang
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Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution
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pp. 430-435
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Bao Liu
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Defect characterization in magnetic field coupled arrays
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pp. 436-441
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Anita Kumari
,
Javier F. Pulecio
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Sanjukta Bhanja
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CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design
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pp. 442-446
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Akif Sultan
,
John Faricelli
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Sushant Suryagandh
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Hans vanMeer
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Kaveri Mathur
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James Pattison
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Sean Hannon
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Greg Constant
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Kalyana Kumar
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Kevin Carrejo
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Joe Meier
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Rasit O. Topaloglu
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Darin Chan
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Uwe Hahn
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Thorsten Knopp
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Victor Andrade
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Bill Gardiol
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Steve Hejl
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David Wu
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James Buller
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Larry Bair
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Ali Icel
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Yuri Apanovich
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A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications
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pp. 447-450
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Maruthi Chandrasekhar Bh
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Sudeb Dasgupta
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Design methodology of high performance on-chip global interconnect using terminated transmission-line
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pp. 451-458
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Yulei Zhang
,
Ling Zhang
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Alina Deutsch
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George A. Katopis
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Daniel M. Dreps
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James F. Buckwalter
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Ernest S. Kuh
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Chung-Kuan Cheng
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New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs
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pp. 459-464
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Ji-Hye Bong
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Yong-Jin Kwon
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Kyeong-Sik Min
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Sung-Mo Kang
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Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit
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pp. 465-470
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Xin He
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Syed Al-Kadry
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Afshin Abdollahi
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Standby power reduction and SRAM cell optimization for 65nm technology
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pp. 471-475
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S. Lakshminarayanan
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J. Joung
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G. Narasimhan
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R. Kapre
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M. Slanina
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J. Tung
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M. Whately
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C-L. Hou
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W-J. Liao
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S-C. Lin
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P-G. Ma
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C-W. Fan
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M-C. Hsieh
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F-C. Liu
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K-L. Yeh
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W-C. Tseng
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S.W. Lu
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Optimization strategies to improve statistical timing
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pp. 476-481
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Parimala Viswanath
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Pranav Murthy
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Debajit Das
,
R. Venkatraman
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Ajoy Mandal
,
Arvind Veeravalli
,
Udayakumar H
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Clock gating effectiveness metrics: Applications to power optimization
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pp. 482-487
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Jithendra Srinivas
,
Madhusudan Rao
,
S. Jairam
,
H. Udayakumar
,
Jagdish Rao
Papers
Buffer/flip-flop block planning for power-integrity-driven floorplanning
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pp. 488-493
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Hsin-Hua Pan
,
Hung-Ming Chen
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Chia-Yi Chang
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On temperature planarization effect of copper dummy fills in deep nanometer technology
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pp. 494-499
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Basab Datta
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Wayne Burleson
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Fast characterization of parameterized cell library
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pp. 500-505
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Uday Doddannagari
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Shiyan Hu
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Weiping Shi
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Cell shifting aware of wirelength and overlap
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pp. 506-510
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Liu Dawei
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Qiang Zhou
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Jinian Bian
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Yici Cai
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Xianlong Hong
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Lagrangian relaxation based register placement for high-performance circuits
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pp. 511-516
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Mei-Fang Chiang
,
Takumi Okamoto
,
Takeshi Yoshimura
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Implementation of power managed hyper transport system for transmission of HD video
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pp. 517-521
by
Adithya V. Kodati
,
Koneswara S. Vemuri
,
Lili He
,
Morris Jones
Papers
Power aware placement for FPGAs with dual supply voltages
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pp. 522-526
by
Zohreh Karimi
,
Majid Sarrafzadeh
Papers
VLSI architectures of perceptual based video watermarking for real-time copyright protection
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pp. 527-534
by
Saraju P. Mohanty
,
Elias Kougianos
,
Wei Cai
,
Manish Ratnani
Papers
VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models
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pp. 535-540
by
Shu-Hsuan Chou
,
Che-Neng Wen
,
Yan-Ling Liu
,
Tien-Fu Chen
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