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Proceedings
LATS
LATS 2015
Generate Citations
2015 16th Latin-American Test Symposium (LATS)
March 25 2015 to March 27 2015
Puerto Vallarta, Mexico
Table of Contents
Message from the LATS2015 Chairs
Freely available from IEEE.
pp. 1-1
by
Victor Champac
,
Yervant Zorian
,
Leticia Bolzani Pohls
,
Vishwani Agrawal
LATS2015 Committees
Freely available from IEEE.
pp. 1-3
Table of contents (technical program)
Freely available from IEEE.
pp. 1-9
[Copyright notice]
Freely available from IEEE.
pp. 1-1
Efficient fault injection in QEMU
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pp. 1-6
by
Davide Ferraretto
,
Graziano Pravadelli
Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs
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pp. 1-6
by
Hiroyuki Yamauchi
,
Worawit Somha
Complex delay fault reasoning with sequential 7-valued algebra
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pp. 1-6
by
Jaak Kousaar
,
Raimund Ubar
,
Igor Aleksejev
Test set generation almost for free using a run-time FPGA reconfiguration technique
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pp. 1-6
by
Alexandra Kourfali
,
Dirk Stroobandt
Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG
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pp. 1-6
by
N. Palermo
,
V. Tihhomirov
,
T.S. Copetti
,
M. Jenihhin
,
J. Raik
,
S. Kostin
,
M. Gaudesi
,
G. Squillero
,
M. Sonza Reorda
,
F. Vargas
,
L. Bolzani Poehls
An evolutionary approach for test program compaction
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pp. 1-6
by
R. Cantoro
,
M. Gaudesi
,
E. Sanchez
,
P. Schiavone
,
G. Squillero
A digital technique for the evaluation of SSB phase noise of analog/RF signals
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pp. 1-6
by
F. Azais
,
S. David-Grignot
,
L. Latorre
,
F. Lefevre
Single event effects in an analog SOI transconductor: a case study
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pp. 1-4
by
Carlos Viale
,
Pablo Petrashin
,
Luis Toledo
,
Walter Lancioni
,
Carlos Vazquez
CMOS amplifier with self-correction offset for SerDes applications
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pp. 1-4
by
Rigoberto Bracamontes-Salazar
,
Esdras Juarez-Hernandez
,
Federico Lobato-Lopez
,
Esteban Martinez-Guerrero
Improving logic obfuscation via logic cone analysis
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pp. 1-6
by
Yu-Wei Lee
,
Nur A. Touba
Virtual reconfigurable scan-chains on FPGAs for optimized board test
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pp. 1-6
by
Igor Aleksejev
,
Sergei Devadze
,
Artur Jutman
,
Konstantin Shibin
A controllable setup and propagation delay flip-flop design
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pp. 1-5
by
Alexandro Giron-Allende
,
Victor Avendano
,
Esteban Martinez-Guerrero
SW-based transparent in-field memory testing
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pp. 1-6
by
Paolo Bernardi
,
Lyl Ciganda
,
Matteo Sonza Reorda
,
Said Hamdioui
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments
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pp. 1-6
by
Jimmy Tarrillo
,
Jorge Tonfat
,
Lucas Tambara
,
Fernanda Lima Kastensmidt
,
Ricardo Reis
Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs
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pp. 1-6
by
Sandeep Kumar Singh
,
Abir J Mondal
,
Alak Majumder
Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability
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pp. 1-6
by
Andres Gomez
,
Victor Champac
Adopting multi-valued logic for reduced pin-count testing
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pp. 1-6
by
Baohu Li
,
Bei Zhang
,
Vishwani D. Agrawal
Design dependent SRAM PUF robustness analysis
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pp. 1-6
by
Mafalda Cortez
,
Said Hamdioui
,
Ryoichi Ishihara
A virtual instrument design for low-cost charge-pumping characterization of integrated MOSFETs
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pp. 1-4
by
Jailene Hernandez
,
Johan Castrillon
,
Manuel Jimenez
,
Angel De La Torre
,
Pedro Escalona
,
Rogelio Palomera
FPGA redundancy recovery based on partial bitstreams for multiple partitions
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pp. 1-4
by
Victor M. Goncalves Martins
,
Joao Gabriel Reis
,
Horacio C. C. Netoy
,
Eduardo Augusto Bezerra
Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver
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pp. 1-4
by
W. Rahajandraibe
,
F. Haddad
,
H. Aziza
,
K. Castellani-Coulie
,
J.-M. Portal
NBTI-induced circuit aging optimization by protectability-aware gate replacement technique
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pp. 1-4
by
Guimao Zhang
,
Maoxiang Yi
,
Yong Miao
,
Dawen Xu
,
Huaguo Liang
Optimizing operational amplifiers by metaheuristics and considering tolerance analysis
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pp. 1-4
by
Luis Gerardo de la Fraga
,
Esteban Tlelo-Cuautle
Study of regression methodologies on analog circuit design
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pp. 1-6
by
Ivick Guerra-Gomez
,
Trent McConaghy
,
E. Tlelo-Cuautle
Rare event diagnosis by iterative failure region locating and elite learning sample selection
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pp. 1-5
by
Hosoon Shin
,
Sheldon X.-D. Tan
,
Guoyong Shi
,
Esteban Tlelo-Cuautle
Optimizing an LDO voltage regulator by evolutionary algorithms considering tolerances of the circuit elements
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pp. 1-5
by
Jesus Lopez-Arredondo
,
Esteban Tlelo-Cuautle
,
Rodolfo Trejo-Guerra
Fault conditions of a simple chaotic circuit under capacitor nonlinear effects
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pp. 1-5
by
J.L. Bueno-Ruiz
,
C.A. Arriaga-Arriaga
,
R. Huerta-Barrera
,
G.V. Cruz-Dominguez
,
C.H. Pimentel-Romero
,
J.M. Munoz-Pacheco
,
L.C. Gomez-Pavon
,
O. Felix-Beltran
,
A. Luis-Ramos
A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems
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pp. 1-6
by
S. Müller
,
T. Koal
,
S. Scharoba
,
H.T. Vierhaus
,
M. Schölzel
Considerations on application of selective hardening based on software fault tolerance techniques
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pp. 1-6
by
Felipe Restrepo-Calle
,
Sergio Cuenca-Asensi
,
Antonio Martínez-Alvarez
,
Fernanda Lima Kastensmidt
Test compression for circuits with multiple scan chains
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pp. 1-6
by
Ondrej Novak
,
Jiri Jenícek
,
Martin Rozkovec
"Safe" built-in test and tuning of boost converters using feedback loop perturbations
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pp. 1-6
by
X. Wang
,
K. Blanchard
,
S. Estella
,
A. Chatterjee
A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults
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pp. 1-6
by
Takanori Moriyasu
,
Satoshi Ohtake
Improvement of a detection chain based on a VCO concept for microelectronic reliability under natural radiative environment
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pp. 1-5
by
K. Coulie-Castellani
,
W. Rahajandraibe
,
H. Aziza
,
J.-M. Portal
,
G. Micolau
Impedance matching analysis and EMC validation of a low-cost PCB differential interconnect
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pp. 1-5
by
J. Rafael Del-rey
,
Zabdiel Brito-Brito
,
Jose E. Rayas-sanchez
Noise analysis of integrated bulk current sensors for detection of radiation induced soft errors
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pp. 1-6
by
Joao Guilherme Mourao Melo
,
Frank Sill Torres
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell
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pp. 1-6
by
Hector Villacorta
,
Roberto Gomez
,
Sebastia Bota
,
Jaume Segura
,
Victor Champac
Power distribution network analysis using semi irregular plane shape approach and via modeling
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pp. 1-6
by
Antonio Zenteno Ramirez
Transformations on the FSMD of the RTL code with combinational logic statements for equivalence checking of HLS
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pp. 1-6
by
Raul Acosta Hernandez
,
Marius Strum
,
Wang Jiang Chau
Vericonn: a tool to generate efficient interconnection networks for post-silicon debug
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pp. 1-6
by
Andre B. M. Gomes
,
Fredy A. M. Alves
,
Ricardo S. Ferreira
,
Jose Augusto M. Nacif
Estimation of dynamic current waveforms using pre-characterization of standard cells
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pp. 1-6
by
Bharath Shivashankar
,
Michael Skaggs
,
Sushmita Kadiyala Rao
,
Ryan Robucci
,
Nilanjan Banerjee
,
Chintan Patel
Exemplar-based failure triage for regression design debugging
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pp. 1-6
by
Zissis Poulos
,
Andreas Veneris
Using only redundant modules with approximate logic to reduce drastically area overhead in TMR
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pp. 1-6
by
Iuri A. C. Gomes
,
Mayler Martins
,
Andre Reis
,
Fernanda Lima Kastensmidt
Fault-tolerance in FPGA focusing power reduction or performance enhancement
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pp. 1-6
by
C. Leong
,
J. Semiao
,
M.B. Santos
,
I.C. Teixeira
,
J.P. Teixeira
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture
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pp. 1-6
by
Ronaldo R. Ferreira
,
Ernesto Sanchez
,
Jean Da Rolt
,
Gabrie L. Nazar
,
Alvaro F. Moreira
,
Luigi Carro
,
Matteo Sonza Reorda
NBTI-aware design of integrated circuits: a hardware-based approach
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pp. 1-6
by
T. Copetti
,
G. Cardoso Medeiros
,
L. Bolzani Poehls
,
F. Vargas
Scan based two-pattern tests: should they target opens instead of TDFs?
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pp. 1-2
by
Adit D. Singh
Design of ultra-low-power smart wearable systems
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pp. 1-2
by
Gregoire Surrel
,
Francisco Rincon
,
Srinivasan Murali
,
David Atienza
In-field test of safety-critical systems: is functional test a feasible solution?
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pp. 1-2
by
Matteo Sonza Reorda
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