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2007 IEEE/ACM International Conference on Computer Aided Design

Nov. 4 2007 to Nov. 8 2007

San Jose, CA

Table of Contents

IntroductionFreely available from IEEE.
Conference committeeFreely available from IEEE.pp. iii-vii
ForewordFreely available from IEEE.
A fast and high-capacity electromagnetic solution for high- speed IC designFull-text access may be available. Sign in or learn about subscription options.
by Houle Gan, Dan Jiao
Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element methodFull-text access may be available. Sign in or learn about subscription options.
by Yang Yi, Peng Li, Vivek Sarin, Weiping Shi
Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approachFull-text access may be available. Sign in or learn about subscription options.
by Arun V Sathanur, Ritochit Chakraborty, Vikram Jandhyala
Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chipFull-text access may be available. Sign in or learn about subscription options.
by Zhonghai Lu, Axel Jantsch
Run-time adaptive on-chip communication schemeFull-text access may be available. Sign in or learn about subscription options.
by Mohammad Abdullah Al Faruque, Thomas Ebi, Jorg Henkel
Using functional independence conditions to optimize the performance of latency-insensitive systemsFull-text access may be available. Sign in or learn about subscription options.
by Cheng-Hong Li, Luca P. Carloni
A geometric approach for early power grid verification using current constraintsFull-text access may be available. Sign in or learn about subscription options.
by Imad A. Ferzli, Farid N. Najm, Lars Kruse
Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networksFull-text access may be available. Sign in or learn about subscription options.
by Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong
Parallel domain decomposition for simulation of large-scale power gridsFull-text access may be available. Sign in or learn about subscription options.
by Kai Sun, Quming Zhou, Kartik Mohanram, Danny C. Sorensen
Fast exact toffoli network synthesis of reversible logicFull-text access may be available. Sign in or learn about subscription options.pp. 60-64
by Robert Wille, Daniel Grosse
A novel synthesis algorithm for reversible circuitsFull-text access may be available. Sign in or learn about subscription options.
by Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani
Checking equivalence of quantum circuits and statesFull-text access may be available. Sign in or learn about subscription options.
by George F. Viamontes, Igor L. Markov, John P. Hayes
A self-adjusting clock tree architecture to cope with temperature variationsFull-text access may be available. Sign in or learn about subscription options.
by Jieyi Long, Ja Chun Ku, Seda Ogrenci Memik, Yehea Ismail
Exploiting STI stress for performanceFull-text access may be available. Sign in or learn about subscription options.
by Andrew B. Kahng, Puneet Sharma, Rasit O. Topaloglu
Automating post-silicon debugging and repairFull-text access may be available. Sign in or learn about subscription options.
by Kai-hui Chang, Igor L. Markov, Valeria Bertacco
Practical method for obtaining a feasible integer solution in hierarchical layout optimizationFull-text access may be available. Sign in or learn about subscription options.
by Xiaoping Tang, Xin Yuan, Michael S. Gray
Monte-carlo driven stochastic optimization framework for handling fabrication variabilityFull-text access may be available. Sign in or learn about subscription options.
by Vishal Khandelwal, Ankur Srivastava
Gate sizing by lagrangian relaxation revisitedFull-text access may be available. Sign in or learn about subscription options.
by Jia Wang, Debasish Das, Hai Zhou
An efficient algorithm for statistical circuit optimization using lagrangian relaxationFull-text access may be available. Sign in or learn about subscription options.
by I-Jye Lin, Yao-Wen Chang
Unified adaptivity optimization of clock and logic signalsFull-text access may be available. Sign in or learn about subscription options.
by Shiyan Hu, Jiang Hu
Incremental component implementation selection: enabling ECO in compositional system synthesisFull-text access may be available. Sign in or learn about subscription options.
by Soheil Ghiasi
Exploiting hierarchy and structure to efficiently solve graph coloring as SATFull-text access may be available. Sign in or learn about subscription options.
by Miroslav N. Velev
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectorsFull-text access may be available. Sign in or learn about subscription options.
by Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon Meredith, Florian Enescu
Enhancing design robustness with reliability-aware resynthesis and logic simulationFull-text access may be available. Sign in or learn about subscription options.
by Smita Krishnaswamy, Stephen M. Plaza, Igor L. Markov, John P. Hayes
Data locality enhancement for CMPsFull-text access may be available. Sign in or learn about subscription options.
by Mahmut Kandemir
Mapping model with Inter-array memory sharing for multidimensional signal processingFull-text access may be available. Sign in or learn about subscription options.
by Ilie I. Luican, Hongwei Zhu, Florin Balasa
Increasing data-bandwidth to instruction-set extensions through register clusteringFull-text access may be available. Sign in or learn about subscription options.
by Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP designFull-text access may be available. Sign in or learn about subscription options.
by Philip Brisk, Ajay K. Verma, Paolo Ienne
An efficient algorithm for time separation of events in concurrent systemsFull-text access may be available. Sign in or learn about subscription options.
by Peggy B. McGee, Steven M. Nowick
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gatesFull-text access may be available. Sign in or learn about subscription options.
by Yu Hu, Satyaki Das, Steve Trimberger, Lei He
Device and architecture concurrent optimization for FPGA transient soft error rateFull-text access may be available. Sign in or learn about subscription options.
by Yan Lin, Lei He
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filteringFull-text access may be available. Sign in or learn about subscription options.
by Georgios Karakonstantis, Nilanjan Banerjee, Kaushik Roy, Chaitali Chakrabarti
Thermal-aware steiner routing for 3D stacked ICsFull-text access may be available. Sign in or learn about subscription options.
by Mohit Pathak, Sung Kyu Lim
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffsFull-text access may be available. Sign in or learn about subscription options.
by Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen
Strategies for improving the parametric yield and profits of 3D ICsFull-text access may be available. Sign in or learn about subscription options.
by Cesare Ferri, Sherief Reda, R. Iris Bahar
Scalable exploration of functional dependency by interpolation and incremental SAT solvingFull-text access may be available. Sign in or learn about subscription options.pp. 227-233
by Chih-Chun Lee, J.-H.R. Jiang, Chung-Yang Huang, A. Mishchenko
Incremental learning approach and SAT model for boolean matching with don’t caresFull-text access may be available. Sign in or learn about subscription options.
by Kuo-Hua Wang, Chung-Ming Chan
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and testFull-text access may be available. Sign in or learn about subscription options.
by Hratch Mangassarian, Andreas Veneris, Sean Safarpour, Marco Benedetti, Duncan Smith
The coming of age of physical synthesisFull-text access may be available. Sign in or learn about subscription options.
by Charles J. Alpert, Chris Chu, Paul G. Villarrubia
An incremental learning framework for estimating signal controllability in unit-level verificationFull-text access may be available. Sign in or learn about subscription options.
by Charles H.-P. Wen, Li-C. Wang, Jayanta Bhadra
Stimulus generation for constrained random simulationFull-text access may be available. Sign in or learn about subscription options.
by Nathan Kitchen, Andreas Kuehlmann
Probabilistic decision diagrams for exact probabilistic analysisFull-text access may be available. Sign in or learn about subscription options.
by Afshin Abdollahi
Computation of minimal counterexamples by using black box techniques and symbolic methodsFull-text access may be available. Sign in or learn about subscription options.
by Tobias Nopper, Christoph Scholl, Bernd Becker
Approximation algorithm for the temperature-aware scheduling problemFull-text access may be available. Sign in or learn about subscription options.
by Sushu Zhang, Karam S. Chatha
Procrastination determination for periodic real-time tasks in leakage-aware dynamic voltage scaling systems.Full-text access may be available. Sign in or learn about subscription options.
by Jian-Jia Chen, Tei-Wei Kuo
The FAST methodology for high-speed SoC/computer simulationFull-text access may be available. Sign in or learn about subscription options.
by Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil Patil, William H. Reinhart, D. Eric Johnson, Zheng Xu
A novel SoC design methodology combining adaptive software and reconfigurable hardwareFull-text access may be available. Sign in or learn about subscription options.
by Marco D. Santambrogio, Vincenzo Rana, Seda Ogrenci Memik, Umut A. Acar, Donatella Sciuto
Can nano-photonic silicon circuits become an INTRA-chip interconnect technology?Full-text access may be available. Sign in or learn about subscription options.
by Eli Yablonovitch
Hybrid cegar: combining variable hiding and predicate abstractionFull-text access may be available. Sign in or learn about subscription options.
by Chao Wang, Hyondeuk Kim, Aarti Gupta
Automated refinement checking of concurrent systemsFull-text access may be available. Sign in or learn about subscription options.
by Sudipta Kundu, Sorin Lerner, Rajesh Gupta
Inductive equivalence checking under retiming and resynthesisFull-text access may be available. Sign in or learn about subscription options.
by Jie-Hong R. Jiang, Wei-Lun Hung
A frequency-domain technique for statistical timing analysis of clock meshesFull-text access may be available. Sign in or learn about subscription options.
by Ruilin Wang, Cheng-Kok Koh
Clustering based pruning for statistical criticality computation under process variationsFull-text access may be available. Sign in or learn about subscription options.
by Hushrav D Mogal, Haifeng Qian, Sachin S Sapatnekar, Kia Bazargan
Timing budgeting under arbitrary process variationsFull-text access may be available. Sign in or learn about subscription options.
by Ruiming Chen, Hai Zhou
Exploiting symmetry in SAT-based boolean matching for heterogeneous FPGA technology mappingFull-text access may be available. Sign in or learn about subscription options.
by Yu Hu, Victor Shih, Rupak Majumdar, Lei He
Combinational and sequential mapping with priority cutsFull-text access may be available. Sign in or learn about subscription options.
by Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert Brayton
A general model for performance optimization of sequential systemsFull-text access may be available. Sign in or learn about subscription options.
by Dmitry Bufistov, Jordi Cortadella, Mike Kishinevsky, Sachin Sapatnekar
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domainsFull-text access may be available. Sign in or learn about subscription options.
by Lei Cheng, Deming Chen, Martin D.F. Wong, Mike Hutton, Jason Govig
Skew aware polarity assignment in clock treeFull-text access may be available. Sign in or learn about subscription options.
by Po-Yuan Chen, Kuan-Hsien Ho, TingTing Hwang
Efficient multi-layer obstacle-avoiding rectilinear steiner tree constructionFull-text access may be available. Sign in or learn about subscription options.
by Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Li, Yao-Wen Chang
A simultaneous bus orientation and bused pin flipping algorithmFull-text access may be available. Sign in or learn about subscription options.
by Fan Mo, Robert K. Brayton
Optimal bus sequencing for escape routing in dense PCBsFull-text access may be available. Sign in or learn about subscription options.
by Hui Kong, Tan Yan, Martin D.F. Wong, Muhammet Mustafa Ozdal
Untangling twisted nets for bus routingFull-text access may be available. Sign in or learn about subscription options.
by Tan Yan, Martin D.F. Wong
Low-overhead design technique for calibration of maximum frequency at multiple operating pointsFull-text access may be available. Sign in or learn about subscription options.
by Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia
Variation-aware performance verification using at-speed structural test and statistical timingFull-text access may be available. Sign in or learn about subscription options.
by Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David Lackey, Peter Habitz, Chandu Visweswariah
Estimation of delay test quality and its application to test generationFull-text access may be available. Sign in or learn about subscription options.
by Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo
Efficient path delay test generation based on stuck-at test generation using checker circuitryFull-text access may be available. Sign in or learn about subscription options.
by Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
Timing variation-aware high-level synthesisFull-text access may be available. Sign in or learn about subscription options.
by Jongyoon Jung, Taewhan Kim
Early planning for clock skew scheduling during register bindingFull-text access may be available. Sign in or learn about subscription options.
by Min Ni, Seda Ogrenci Memik
Compatibility path based binding algorithm for interconnect reduction in high level synthesisFull-text access may be available. Sign in or learn about subscription options.
by Taemin Kim, Xun Liu
Operation chaining asynchronous pipelined circuitsFull-text access may be available. Sign in or learn about subscription options.
by Girish Venkataramani, Seth C. Goldstein
Adaptive post-silicon tuning for analog circuits: concept, analysis and optimizationFull-text access may be available. Sign in or learn about subscription options.
by Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi
Sensitivity analysis for oscillatorsFull-text access may be available. Sign in or learn about subscription options.pp. 458-463
by Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Yield-aware analog integrated circuit optimization using geostatistics motivated performance modelingFull-text access may be available. Sign in or learn about subscription options.
by Guo Yu, Peng Li
Device-circuit co-optimization for mixed-mode circuit design via geometric programmingFull-text access may be available. Sign in or learn about subscription options.
by Jintae Kim, Ritesh Jhaveri, Jason Woo, Chih-Kong Ken Yang
Modeling, optimization and control of rotary traveling-wave oscillatorFull-text access may be available. Sign in or learn about subscription options.
by Cheng Zhuo, Huafeng Zhang, Rupak Samanta, Jiang Hu, Kangsheng Chen
A methodology for fast and accurate yield factor estimation during global routingFull-text access may be available. Sign in or learn about subscription options.
by Subarna Sinha, Charles C. Chiang
Archer: a history-driven global routing algorithmFull-text access may be available. Sign in or learn about subscription options.
by Muhammet Mustafa Ozdal, Martin D. F. Wong
High-performance routing at the nanometer scaleFull-text access may be available. Sign in or learn about subscription options.
by Jarrod A. Roy, Igor L. Markov
BoxRouter 2.0: architecture and implementation of a hybrid and robust global routerFull-text access may be available. Sign in or learn about subscription options.
by Minsik Cho, Katrina Lu, Kun Yuan, David Z. Pan
Cachecompress: a novel approach for test data compression with cache for IP embedded coresFull-text access may be available. Sign in or learn about subscription options.
by Hao Fang, Chenguang Tong, Bo Yao, Xiaodi Song, Xu Cheng
A hybrid scheme for compacting test responses with unknown valuesFull-text access may be available. Sign in or learn about subscription options.
by Mango C.-T. Chao, Kwang-Ting Cheng, Seongmoon Wang, Srimat T. Chakradhar, Wen-Long Wei
A selective pattern-compression scheme for power and test-data reductionFull-text access may be available. Sign in or learn about subscription options.
by Chia-Yi Lin, Hung-Ming Chen
Methodology for low power test pattern generation using activity threshold control logicFull-text access may be available. Sign in or learn about subscription options.
by Srivaths Ravi, V. R. Devanathan, Rubin Parekhji
ECO timing optimization using spare cellsFull-text access may be available. Sign in or learn about subscription options.
by Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang
Timing optimization by restructuring long combinatorial pathsFull-text access may be available. Sign in or learn about subscription options.
by Jeurgen Werber, Dieter Rautenbach, Christian Szegedy
Engineering change using spare cells with constant insertionFull-text access may be available. Sign in or learn about subscription options.pp. 544-547
by Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Marek-Sadowska Malgorzata
Simultaneous input vector selection and dual threshold voltage assignment for static leakage minimizationFull-text access may be available. Sign in or learn about subscription options.
by Lin Yuan, Gang Qu
Equalized interconnects for on-chip networks: modeling and optimization frameworkFull-text access may be available. Sign in or learn about subscription options.
by Byungsub Kim, Vladimir Stojanovic
Intsim: a CAD tool for optimization of multilevel interconnect networksFull-text access may be available. Sign in or learn about subscription options.
by Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl
A fast band-matching technique for interconnect inductance modelingFull-text access may be available. Sign in or learn about subscription options.
by Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan
Formal verification at higher levels of abstractionFull-text access may be available. Sign in or learn about subscription options.
by Daniel Kroening, Sanjit A. Seshia
Analog placement with common centroid constraintsFull-text access may be available. Sign in or learn about subscription options.
by Qiang Ma, Evangeline F. Y. Young, K. P. Pun
Temperature aware microprocessor floorplanning considering application dependent power loadFull-text access may be available. Sign in or learn about subscription options.
by Chun-Ta Chu, Xinyi Zhang, Lei He, Tom Tong Jing
3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 590-597
by Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou
Variation-aware task allocation and scheduling for MPSoCFull-text access may be available. Sign in or learn about subscription options.
by Feng Wang, C. Nicopoulos, Xiaoxia Wu, Yuan Xie, N. Vijaykrishnan
A design flow dedicated to multi-mode architectures for DSP applicationsFull-text access may be available. Sign in or learn about subscription options.
by Cyrille Chavet, Caaliph Andriamisaina, Philippe Coussy, Emmanuel Casseau, Emmanuel Juin, Pascal Urard, Eric Martin
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