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Formal Methods and Models for Co-Design, ACM/IEEE International Conference on

June 24 2003 to June 26 2003

Mont Saint-Michel, France

ISBN: 0-7695-1923-7

Table of Contents

Engineering changes in field modifiable architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 87,88,89,90,91,92,93,94
by H. Saito, K. Seto, Y. Kojima, S. Komatsu, M. Fujita
Introduction
Message from the ChairsFreely available from IEEE.pp. viii
Introduction
Committee Members and OrganizersFreely available from IEEE.pp. x
Invited Talk
Executable Computational Logics: Combining Formal Methods and Programming Language Based System DesignFull-text access may be available. Sign in or learn about subscription options.pp. 3
by Jose Meseguer
System Level Models and Co-design
MoDe: A Method for System-Level Architecture EvaluationFull-text access may be available. Sign in or learn about subscription options.pp. 13
by Jan Romberg, Oscar Slotosch Gabor Hahn
Verification of transaction-level SystemC models using RTL testbenchesFull-text access may be available. Sign in or learn about subscription options.pp. 199,200,201,202,203
by R. Jindal, K. Jain
System Level Models and Co-design
From Use Cases to System Implementation: Statechart Based Co-designFull-text access may be available. Sign in or learn about subscription options.pp. 24
by Lu?s Gomes, Anik? Costa
System Level Models and Co-design
Petri Net Based Interface Analysis for Fast IP-Core IntegrationFull-text access may be available. Sign in or learn about subscription options.pp. 34
by Julio A. de Oliveira Filho, Manoel E. de Lima, Paulo Romero Maciel
Short Presentation Session
Goal-Oriented Requirements Analysis for Process Control Systems DesignFull-text access may be available. Sign in or learn about subscription options.pp. 45
by Islam El-Maddah, Tom Maibaum
Short Presentation Session
Analyzing Concurrency in Computational NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 47
by Sander Stuijk, Twan Basten
Short Presentation Session
Translating Fusion/UML to Object-ZFull-text access may be available. Sign in or learn about subscription options.pp. 49
by Margot Bittner, Florian Kammller
Short Presentation Session
Finding Good Counter-Examples to Aid Design VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 51
by Goerschwin Fey, Rolf Drechsler
Formal Verification I
High Level Verification of Control Intensive Systems Using Predicate AbstractionFull-text access may be available. Sign in or learn about subscription options.pp. 55
by Edmund Clarke, Orna Grumberg, Muralidhar Talupur, Dong Wang
Formal Verification I
Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory ExceptionsFull-text access may be available. Sign in or learn about subscription options.pp. 65
by Sudarshan K. Srinivasan, Miroslav N. Velev
Formal Verification I
Combining ACL2 and a v-calculus Model-Checker to Verify System-Level DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 75
by Magali Contensin, Laurence Pierre
Field Modifiability and Verifiability
Engineering Changes in Field Modifiable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 87
Panel I
Hierarchical and Incremental Verification for System Level Design: Challenges and AccomplishmentsFull-text access may be available. Sign in or learn about subscription options.pp. 97
by Grant Martin, Sandeep Shukla
Refinement/Conformance I
How to Compute the Refinement Relation for Parameterized SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 103
by Francoise Bellegarde, Celina Charlet, Olga Kouchnarenko
Refinement/Conformance I
Using SSDE for USB2.0 conformance co-verificationFull-text access may be available. Sign in or learn about subscription options.pp. 113
by Thierry J-F. Omnes, Gerard Postuma, Jos Verhaegh, Marleen Boonen, Nick Gatherer
Refinement/Conformance I
From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs TransformationsFull-text access may be available. Sign in or learn about subscription options.pp. 123
by Thierry Grandpierre, Yves Sorel
Invited Talk
Methods for exploiting SAT solvers in unbounded model checkingFull-text access may be available. Sign in or learn about subscription options.pp. 135
by K. L. McMillan
Validation, Co-validation
On the Use of a High-Level Fault Model to Check Properties IncompletenessFull-text access may be available. Sign in or learn about subscription options.pp. 145
by Franco Fummi, Graziano Pravadelli, Andrea Fedeli, Umberto Rossi, Franco Toto
Validation, Co-validation
Exact Runtime Analysis Using Automata-Based Symbolic SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 153
by Tobias Sch?, Klaus Schneider
Validation, Co-validation
Real-time Property Preservation in Approximations of Timed SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 163
by Jinfeng Huang, Jeroen Voeten, Marc Geilen
Validation, Co-validation
Reliability Evaluation for Dependable Embedded System Specifications: An Approach Based on DSPNFull-text access may be available. Sign in or learn about subscription options.pp. 172
by S?rgio M.M. Fernandes, Paulo R. M. Maciel
Invited Talk
Modular Hierarchies of Models for Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 183
by Manfred BROY
Refinement II
Verification of Transaction-Level SystemC models using RTL TestbenchesFull-text access may be available. Sign in or learn about subscription options.pp. 199
Refinement II
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnectFull-text access may be available. Sign in or learn about subscription options.pp. 204
by Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, Richard Hersemeule, Jean-Philippe Cousin
Synthesis, Optimization
A Generalised Approach to Supervisor SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 217
by Roberto Ziller, Klaus Schneider
Synthesis, Optimization
Optimizations for Faster Execution of Esterel ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 227
by Dumitru Potop-Butucaru, Robert de Simone
Synthesis, Optimization
Bridging CSP and C++ with Selective Formalism and Executable SpecificationsFull-text access may be available. Sign in or learn about subscription options.pp. 237
by W. B. Gardner
Invited Talk
Bluespec: A language for hardware design, simulation, synthesis and verification Invited TalkFull-text access may be available. Sign in or learn about subscription options.pp. 249
by Arvind
Formal Verification II
A Verification Methodology for Infinite-State Message Passing SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 255
by Christoph Sprenger, Krzysztof Worytkiewicz
Formal Verification II
Verification of Control Properties in the Polyhedral ModelFull-text access may be available. Sign in or learn about subscription options.pp. 265
by David Cachera, Katell Morin-Allory
Panel II
PANEL: Should the space of implementation possibilities be determined by the abilities of high-level synthesis and validation?Full-text access may be available. Sign in or learn about subscription options.pp. 277
by Rajesh Gupta, Sandeep Shukla
Closing Talk
Robust System Design with Uncertain InformationFull-text access may be available. Sign in or learn about subscription options.pp. 283
by Giovanni De Micheli
Author Index
Author IndexFreely available from IEEE.pp. 285
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