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Formal Methods and Models for Co-Design, ACM/IEEE International Conference on

July 27 2006 to July 30 2006

Napa, CA, USA

ISBN: 1-4244-0421-5

Table of Contents

Papers
Proceedings. Fourth ACM & IEEE International Conference on Formal Methods and Models for Co-Design. (MEMOCODE'06) (IEEE Cat. No. 06EX1398)Full-text access may be available. Sign in or learn about subscription options.pp. i
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CopyrightFull-text access may be available. Sign in or learn about subscription options.pp. ii
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Message from the ChairsFull-text access may be available. Sign in or learn about subscription options.pp. iii
by R.K. Gupta, J.C. Hoe, J. Palsberg
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Organizers and Program Committee MembersFull-text access may be available. Sign in or learn about subscription options.pp. iv
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Table of ContentsFull-text access may be available. Sign in or learn about subscription options.pp. v-viii
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Keynote Talk IFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
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Games for formal design and verification of reactive systemsFull-text access may be available. Sign in or learn about subscription options.pp. 3-4
by R. Alur
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Session I: Model CheckingFull-text access may be available. Sign in or learn about subscription options.pp. 5-6
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Analyzing tabular requirements specifications using infinite state model checkingFull-text access may be available. Sign in or learn about subscription options.pp. 7-16
by T. Bultan, C. Heitmeyer
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Mixed symbolic representations for model checking software programsFull-text access may be available. Sign in or learn about subscription options.pp. 17-26
by Zijiang Yang, Chao Wang, A. Gupta, F. Ivancic
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Component-based hardware/software co-verificationFull-text access may be available. Sign in or learn about subscription options.pp. 27-36
by Fei Xie, Guowu Yang, Xiaoyu Song
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Session II: Rule-based HW DesignFull-text access may be available. Sign in or learn about subscription options.pp. 37-38
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A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-designFull-text access may be available. Sign in or learn about subscription options.pp. 39-48
by H.D. Patel, S.K. Shukla, E. Mednick, R.S. Nikhil
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Low-power hardware synthesis from TRS-based specificationsFull-text access may be available. Sign in or learn about subscription options.pp. 49-58
by G. Singh, S.K. Shukla
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802.11a transmitter: a case study in microarchitectural explorationFull-text access may be available. Sign in or learn about subscription options.pp. 59-68
by N. Dave, M. Pellauer, S. Gerding, Arvind
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Session III: HW VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 69-70
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Automatic decomposition for sequential equivalence checking of system level and RTL descriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 71-80
by S. Vasudevan, J.A. Abraham, V. Viswanath, Jiajin Tu
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A verified development of hardware using CSP/spl par/BFull-text access may be available. Sign in or learn about subscription options.pp. 81-82
by A.A. McEwan, S. Schneider
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Panel I: Nano-Computing: Do we need New Formal Approaches to Co-Design?Full-text access may be available. Sign in or learn about subscription options.pp. 83-84
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Panel: Nano-computing - do we need new formal approaches ?Full-text access may be available. Sign in or learn about subscription options.pp. 85-86
by M. Hsiao, S. Shukla, M. Gokhale, A. Lebeck
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Keynote Talk IIFull-text access may be available. Sign in or learn about subscription options.pp. 87-88
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Scalable program analysis using Boolean satisfiabilityFull-text access may be available. Sign in or learn about subscription options.pp. 89-90
by A. Aiken
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Session IV: Transaction-level ModelingFull-text access may be available. Sign in or learn about subscription options.pp. 91-92
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Execution semantics and formalisms for multi-abstraction TLM assertionsFull-text access may be available. Sign in or learn about subscription options.pp. 93-102
by W. Ecker, V. Esen, M. Hull
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A methodology for abstracting RTL designs into TL descriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 103-112
by N. Bombieri, F. Fummi, G. Pravadelli
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Using Reo for formal specification and verification of system designsFull-text access may be available. Sign in or learn about subscription options.pp. 113-122
by N. Razavi, M. Sirjani
A semantic-driven synthesis flow for platform-based designFull-text access may be available. Sign in or learn about subscription options.pp. 199-199
by Qi Zhu, A. Davare, A. Sangiovanni-Vincentelli
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Panel II: Programming Models and Languages for SOC-Implemented ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 123-124
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Programming models and languages for SoC-implemented architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 125-126
by R. Gupta
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Session V: Time and ClocksFull-text access may be available. Sign in or learn about subscription options.pp. 127-128
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Specifying and proving properties of timed I/O automata in the TIOA toolkitFull-text access may be available. Sign in or learn about subscription options.pp. 129-138
by M. Archer, HongPing Lim, N. Lynch, S. Mitra, S. Umeno
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Reliable design with multiple clock domainsFull-text access may be available. Sign in or learn about subscription options.pp. 139-148
by E. Czeck, R. Nanavati, J. Stoy
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The SystemJ approach to system-level designFull-text access may be available. Sign in or learn about subscription options.pp. 149-158
by F. Gruian, P. Roop, Z. Salcic, I. Radojevic
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Keynote Talk IIIFull-text access may be available. Sign in or learn about subscription options.pp. 159-160
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Integrating design and verification - from simple idea to practical systemFull-text access may be available. Sign in or learn about subscription options.pp. 161-162
by C. Seger
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Session VI: Scheduling and AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 163-164
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Efficient code generation from synchronous programsFull-text access may be available. Sign in or learn about subscription options.pp. 165-174
by K. Schneider, J. Brandt, E. Vecchie
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Latency-insensitive design and central repetitive schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 175-183
by J. Boucaron, R. de Simone, J.-V. Millo
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A scenario-aware data flow model for combined long-run average and worst-case performance analysisFull-text access may be available. Sign in or learn about subscription options.pp. 185-194
by B.D. Theelen, M.C.W. Geilen, T. Basten, J.P.M. Voeten, S.V. Gheorghita, S. Stuijk
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Equivalence checking: a rule-based approachFull-text access may be available. Sign in or learn about subscription options.pp. 197
by M. Fujita, S. Shankar, S. Shunsuke
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Formal methods for checking realizability of coalitions in 3-party systemsFull-text access may be available. Sign in or learn about subscription options.pp. 198
by A. Banerjee, P. Dasgupta, P.P. Chakrabarti
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Assertion checking of control dominated systems with nonlinear solversFull-text access may be available. Sign in or learn about subscription options.pp. 200
by I. Ugarte, P. Sanchez
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Compositional interaction specifications for SystemCFull-text access may be available. Sign in or learn about subscription options.pp. 201
by F. Doucet, I.H. Krueger, R. Gupta, R.K. Shyamasundar
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R-SHIM: deterministic concurrency with recursion and shared variablesFull-text access may be available. Sign in or learn about subscription options.pp. 202
by O. Tardieu, S.A. Edwards
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Author IndexFull-text access may be available. Sign in or learn about subscription options.pp. 203-204
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