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Networks-on-Chip, International Symposium on

May 10 2009 to May 13 2009

La Jolla, CA, USA

ISBN: 978-1-4244-4142-6

Table of Contents

Papers
3rd ACM/IEEE international symposium on networks-on-chipFreely available from IEEE.pp. I
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3rd ACM/IEEE international symposium on networks-on-chipFreely available from IEEE.pp. i
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CopyrightFreely available from IEEE.pp. ii
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Organizing committeeFreely available from IEEE.pp. iii
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Program committeeFreely available from IEEE.pp. iv
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Steering committeeFreely available from IEEE.pp. v
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Additional reviewersFreely available from IEEE.pp. vi
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Message from the chairsFreely available from IEEE.pp. vii
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Table of contentsFreely available from IEEE.pp. viii-xi
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HiRA: A methodology for deadlock free routing in hierarchical networks on chipFull-text access may be available. Sign in or learn about subscription options.pp. 2-11
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Using adaptive routing to compensate for performance heterogeneityFull-text access may be available. Sign in or learn about subscription options.pp. 12-21
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Fault-tolerant architecture and deflection routing for degradable NoC switchesFull-text access may be available. Sign in or learn about subscription options.pp. 22-31
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Adaptive stochastic routing in fault-tolerant on-chip networksFull-text access may be available. Sign in or learn about subscription options.pp. 32-37
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Static virtual channel allocation in oblivious routingFull-text access may be available. Sign in or learn about subscription options.pp. 38-43
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Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chipFull-text access may be available. Sign in or learn about subscription options.pp. 44-53
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Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect linksFull-text access may be available. Sign in or learn about subscription options.pp. 54-63
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Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 64-73
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Analytical modeling and evaluation of On-Chip Interconnects using Network CalculusFull-text access may be available. Sign in or learn about subscription options.pp. 74-79
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Energy efficient application mapping to NoC processing elements operating at multiple voltage levelsFull-text access may be available. Sign in or learn about subscription options.pp. 80-85
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The design of a latency constrained, power optimized NoC for a 4G SoCFull-text access may be available. Sign in or learn about subscription options.pp. 86
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Performance Evaluation of NoC Architectures for Parallel WorkloadsFull-text access may be available. Sign in or learn about subscription options.pp. 87
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Packet-level static timing analysis for NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 88
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Increasing NoC power estimation accuracy through a rate-based modelFull-text access may be available. Sign in or learn about subscription options.pp. 89
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On-Chip photonic interconnects for scalable multi-core architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 90
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A Modeling and exploration framework for interconnect network design in the nanometer eraFull-text access may be available. Sign in or learn about subscription options.pp. 91
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Power reduction through physical placement of asynchronous routersFull-text access may be available. Sign in or learn about subscription options.pp. 92
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Networks-on-chip in emerging interconnect paradigms: Advantages and challengesFull-text access may be available. Sign in or learn about subscription options.pp. 93-102
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Silicon-photonic clos networks for global on-chip communicationFull-text access may be available. Sign in or learn about subscription options.pp. 124-133
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Contention-free on-chip routing of optical packetsFull-text access may be available. Sign in or learn about subscription options.pp. 134-143
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Connection-centric network for spiking neural networksFull-text access may be available. Sign in or learn about subscription options.pp. 144-152
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A Communication and configuration controller for NoC based reconfigurable data flow architectureFull-text access may be available. Sign in or learn about subscription options.pp. 153-162
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Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regionsFull-text access may be available. Sign in or learn about subscription options.pp. 163-172
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Best of both worlds: A bus enhanced NoC (BENoC)Full-text access may be available. Sign in or learn about subscription options.pp. 173-182
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Flow-aware allocation for on-chip networksFull-text access may be available. Sign in or learn about subscription options.pp. 183-192
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CTC: An end-to-end flow control protocol for multi-core systems-on-chipFull-text access may be available. Sign in or learn about subscription options.pp. 193-202
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Performance and power efficient on-chip communication using adaptive virtual point-to-point connectionsFull-text access may be available. Sign in or learn about subscription options.pp. 203-212
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Keynote 3 (Banquet Talk) Digital spaceFreely available from IEEE.pp. 213
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A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection networkFull-text access may be available. Sign in or learn about subscription options.pp. 214-223
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A modular synchronizing FIFO for NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 224-233
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Estimating reliability and throughput of source-synchronous wave-pipelined interconnectFull-text access may be available. Sign in or learn about subscription options.pp. 234-243
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Dynamic packet fragmentation for increased virtual channel utilization in on-chip routersFull-text access may be available. Sign in or learn about subscription options.pp. 250-255
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Diagnosis of interconnect shorts in mesh NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 256-265
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BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channelFull-text access may be available. Sign in or learn about subscription options.pp. 266-275
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Exploring concentration and channel slicing in on-chip network routerFull-text access may be available. Sign in or learn about subscription options.pp. 276-285
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Author indexFreely available from IEEE.pp. 286-287
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