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Proceedings
NOCS
NOCS 2009
Generate Citations
Networks-on-Chip, International Symposium on
May 10 2009 to May 13 2009
La Jolla, CA, USA
ISBN: 978-1-4244-4142-6
Table of Contents
Papers
3rd ACM/IEEE international symposium on networks-on-chip
Freely available from IEEE.
pp. I
Papers
3rd ACM/IEEE international symposium on networks-on-chip
Freely available from IEEE.
pp. i
Papers
Copyright
Freely available from IEEE.
pp. ii
Papers
Organizing committee
Freely available from IEEE.
pp. iii
Papers
Program committee
Freely available from IEEE.
pp. iv
Papers
Steering committee
Freely available from IEEE.
pp. v
Papers
Additional reviewers
Freely available from IEEE.
pp. vi
Papers
Message from the chairs
Freely available from IEEE.
pp. vii
Papers
Table of contents
Freely available from IEEE.
pp. viii-xi
Papers
Keynote 1 NoCs: It is about the memory and the programming model
Freely available from IEEE.
pp. 1
by
Ivo Bolsens
Papers
HiRA: A methodology for deadlock free routing in hierarchical networks on chip
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pp. 2-11
by
Rickard Holsmark
,
Shashi Kumar
,
Maurizio Palesi
,
Andres Mejia
Papers
Using adaptive routing to compensate for performance heterogeneity
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pp. 12-21
by
Yury Markovsky
,
Yatish Patel
,
John Wawrzynek
Papers
Fault-tolerant architecture and deflection routing for degradable NoC switches
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pp. 22-31
by
Adan Kohler
,
Martin Radetzki
Papers
Adaptive stochastic routing in fault-tolerant on-chip networks
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pp. 32-37
by
Wei Song
,
Doug Edwards
,
Jose Luis Nunez-Yanez
,
Sohini Dasgupta
Papers
Static virtual channel allocation in oblivious routing
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pp. 38-43
by
Keun Sup Shim
,
Myong Hyon Cho
,
Michel Kinsy
,
Tina Wen
,
Mieszko Lis
,
G. Edward Suh
,
Srinivas Devadas
Papers
Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip
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pp. 44-53
by
Yue Qian
,
Zhonghai Lu
,
Wenhua Dou
Papers
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
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pp. 54-63
by
Bo Fu
,
David Wolpert
,
Paul Ampadu
Papers
Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip
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pp. 64-73
by
Lei Wang
,
Yuho Jin
,
Hyungjun Kim
,
Eun Jung Kim
Papers
Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
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pp. 74-79
by
M. Bakhouya
,
S. Suboh
,
J. Gaber
,
T. El-Ghazawi
Papers
Energy efficient application mapping to NoC processing elements operating at multiple voltage levels
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pp. 80-85
by
Pavel Ghosh
,
Arunabha Sen
,
Alexander Hall
Papers
The design of a latency constrained, power optimized NoC for a 4G SoC
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pp. 86
by
Rudy Beraha
,
Isask'har Walter
,
Israel Cidon
,
Avinoam Kolodny
Papers
Performance Evaluation of NoC Architectures for Parallel Workloads
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pp. 87
by
Henrique C. Freitas
,
Marco A. Z. Alves
,
Lucas M. Schnorr
,
Philippe O. A. Navaux
Papers
Packet-level static timing analysis for NoCs
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pp. 88
by
Evgeni Krimer
,
Mattan Erez
,
Isaac Keslassy
,
Avinoam Kolodny
,
Isask'har Walter
Papers
Increasing NoC power estimation accuracy through a rate-based model
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pp. 89
by
Guilherme Guindani
,
Cezar Reinbrecht
,
Thiago R. da Rosa
,
Fernando Moraes
Papers
On-Chip photonic interconnects for scalable multi-core architectures
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pp. 90
by
Avinash Karanth Kodi
,
Randy Morris
,
Ahmed Louri
,
Xiang Zhang
Papers
A Modeling and exploration framework for interconnect network design in the nanometer era
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pp. 91
by
Ajay Joshi
,
Fred Chen
,
Vladimir Stojanovic
Papers
Power reduction through physical placement of asynchronous routers
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pp. 92
by
Daniel Gebhardt
,
Kenneth Stevens
Papers
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
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pp. 93-102
by
Luca P. Carloni
,
Partha Pande
,
Yuan Xie
Papers
Keynote 2 NoC's at the center of chip architecture: Urgent needs (today) and what they must become (future)
Freely available from IEEE.
pp. 103
by
Andrew Chien
Papers
Analysis of photonic networks for a chip multiprocessor using scientific applications
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pp. 104-113
by
Gilbert Hendry
,
Shoaib Kamil
,
Aleksandr Biberman
,
Johnnie Chan
,
Benjamin G. Lee
,
Marghoob Mohiyuddin
,
Ankit Jain
,
Keren Bergman
,
Luca P. Carloni
,
John Kubiatowicz
,
Leonid Oliker
,
John Shalf
Papers
Scalability of network-on-chip communication architecture for 3-D meshes
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pp. 114-123
by
Awet Yemane Weldezion
,
Matt Grange
,
Dinesh Pamunuwa
,
Zhonghai Lu
,
Axel Jantsch
,
Roshan Weerasekera
,
Hannu Tenhunen
Papers
Silicon-photonic clos networks for global on-chip communication
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pp. 124-133
by
Ajay Joshi
,
Christopher Batten
,
Yong-Jin Kwon
,
Scott Beamer
,
Imran Shamim
,
Krste Asanovic
,
Vladimir Stojanovic
Papers
Contention-free on-chip routing of optical packets
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pp. 134-143
by
Somayyeh Koohi
,
Shaahin Hessabi
Papers
Connection-centric network for spiking neural networks
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pp. 144-152
by
Robin Emery
,
Alex Yakovlev
,
Graeme Chester
Papers
A Communication and configuration controller for NoC based reconfigurable data flow architecture
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pp. 153-162
by
Fabien Clermidy
,
Romain Lemaire
,
Yvain Thonnart
,
Pascal Vivet
Papers
Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions
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pp. 163-172
by
Martti Forsell
Papers
Best of both worlds: A bus enhanced NoC (BENoC)
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pp. 173-182
by
Ran Manevich
,
Isask'har Walter
,
Israel Cidon
,
Avinoam Kolodny
Papers
Flow-aware allocation for on-chip networks
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pp. 183-192
by
Arnab Banerjee
,
Simon W. Moore
Papers
CTC: An end-to-end flow control protocol for multi-core systems-on-chip
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pp. 193-202
by
Nicola Concer
,
Luciano Bononi
,
Michael Soulie
,
Riccardo Locatelli
,
Luca P. Carloni
Papers
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections
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pp. 203-212
by
Mehdi Modarressi
,
Hamid Sarbazi-Azad
,
Arash Tavakkol
Papers
Keynote 3 (Banquet Talk) Digital space
Freely available from IEEE.
pp. 213
by
Anant Agarwal
Papers
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
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pp. 214-223
by
Anh T. Tran
,
Dean N. Truong
,
Bevan M. Baas
Papers
A modular synchronizing FIFO for NoCs
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pp. 224-233
by
Tarik Ono
,
Mark Greenstreet
Papers
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect
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pp. 234-243
by
Paul Teehan
,
Guy G.F. Lemieux
,
Mark R. Greenstreet
Papers
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
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pp. 244-249
by
Daniele Ludovici
,
Alessandro Strano
,
Davide Bertozzi
,
Luca Benini
,
Georgi N. Gaydadjiev
Papers
Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers
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pp. 250-255
by
Young Hoon Kang
,
Taek-Jun Kwon
,
Jeff Draper
Papers
Diagnosis of interconnect shorts in mesh NoCs
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pp. 256-265
by
Marcos Herve
,
Erika Cota
,
Fernanda Lima Kastensmidt
,
Marcelo Lubaszewski
Papers
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
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pp. 266-275
by
Ying-Cherng Lan
,
Shih-Hsin Lo
,
Yueh-Chi Lin
,
Yu-Hen Hu
,
Sao-Jie Chen
Papers
Exploring concentration and channel slicing in on-chip network router
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pp. 276-285
by
Prabhat Kumar
,
Yan Pan
,
John Kim
,
Gokhan Memik
,
Alok Choudhary
Papers
Author index
Freely available from IEEE.
pp. 286-287
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