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2011 International Conference on Parallel Architectures and Compilation Techniques

Oct. 10 2011 to Oct. 14 2011

Galveston, Texas USA

ISSN: 1089-795X

ISBN: 978-0-7695-4566-0

Table of Contents

Papers
Title Page iFreely available from IEEE.pp. i
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Title Page iiiFreely available from IEEE.pp. iii
[Copyright notice]Freely available from IEEE.pp. iv-iv
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Table of contentsFreely available from IEEE.pp. v-x
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Message from the General ChairFreely available from IEEE.pp. xi
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Message from the Program ChairFreely available from IEEE.pp. xii
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Conference CommitteesFreely available from IEEE.pp. xiii-xv
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ReviewersFreely available from IEEE.pp. xvi
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A Unified Scheduler for Recursive and Task Dataflow ParallelismFull-text access may be available. Sign in or learn about subscription options.pp. 1-11
by Hans Vandierendonck, George Tzenakis, Dimitrios S. Nikolopoulos
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No More Backstabbing... A Faithful Scheduling Policy for Multithreaded ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 12-21
by Kishore Kumar Pusukuri, Rajiv Gupta, Laxmi N. Bhuyan
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Dynamic Fine-Grain Scheduling of Pipeline ParallelismFull-text access may be available. Sign in or learn about subscription options.pp. 22-32
by Daniel Sanchez, David Lo, Richard M. Yoo, Jeremy Sugerman, Christos Kozyrakis
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SPATL: Honey, I Shrunk the Coherence DirectoryFull-text access may be available. Sign in or learn about subscription options.pp. 33-44
by Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas, Vijayalakshmi Srinivasan
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POPS: Coherence Protocol Optimization for Both Private and Shared DataFull-text access may be available. Sign in or learn about subscription options.pp. 45-55
by Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang
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An OpenCL Framework for Homogeneous Manycores with No Hardware Cache CoherenceFull-text access may be available. Sign in or learn about subscription options.pp. 56-67
by Jun Lee, Jungwon Kim, Junghyun Kim, Sangmin Seo, Jaejin Lee
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Compiling Dynamic Data Structures in Python to Enable the Use of Multi-core and Many-core LibrariesFull-text access may be available. Sign in or learn about subscription options.pp. 68-77
by Bin Ren, Gagan Agrawal
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Efficient Parallel Graph Exploration on Multi-Core CPU and GPUFull-text access may be available. Sign in or learn about subscription options.pp. 78-88
by Sungpack Hong, Tayo Oguntebi, Kunle Olukotun
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A Heterogeneous Parallel Framework for Domain-Specific LanguagesFull-text access may be available. Sign in or learn about subscription options.pp. 89-100
by Kevin J. Brown, Arvind K. Sujeeth, Hyouk Joong Lee, Tiark Rompf, Hassan Chafi, Martin Odersky, Kunle Olukotun
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PEPSC: A Power-Efficient Processor for Scientific ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 101-110
by Ganesh Dasika, Ankit Sethia, Trevor Mudge, Scott Mahlke
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Improving Throughput of Power-Constrained GPUs Using Dynamic Voltage/Frequency and Core ScalingFull-text access may be available. Sign in or learn about subscription options.pp. 111-120
by Jungseob Lee, Vijay Sathisha, Michael Schulte, Katherine Compton, Nam Sung Kim
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Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric MulticoresFull-text access may be available. Sign in or learn about subscription options.pp. 121-130
by Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan
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Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud ComputerFull-text access may be available. Sign in or learn about subscription options.pp. 131-142
by Nikolas Ioannou, Michael Kauschke, Matthias Gries, Marcelo Cintra
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Optimizing Data Layouts for Parallel Computation on MulticoresFull-text access may be available. Sign in or learn about subscription options.pp. 143-154
by Yuanrui Zhang, Wei Ding, Jun Liu, Mahmut Kandemir
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DeNovo: Rethinking the Memory Hierarchy for Disciplined ParallelismFull-text access may be available. Sign in or learn about subscription options.pp. 155-166
by Byn Choi, Rakesh Komuravelli, Hyojin Sung, Robert Smolinski, Nima Honarmand, Sarita V. Adve, Vikram S. Adve, Nicholas P. Carter, Ching-Tsun Chou
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A Hierarchical Approach to Maximizing MapReduce EfficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 167-168
by Zhiwei Xiao, Haibo Chen, Binyu Zang
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Building Retargetable and Efficient Compilers for Multimedia Instruction SetsFull-text access may be available. Sign in or learn about subscription options.pp. 169-170
by Serge Guelton, Adrien Guinet, Ronan Keryell
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Compiler Directed Data Locality Optimization for Multicore ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 171-172
by Wei Ding, Jithendra Srinivas, Mahmut Kandemir, Mustafa Karakoy
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CriticalFault: Amplifying Soft Error Effect Using Vulnerability-Driven InjectionFull-text access may be available. Sign in or learn about subscription options.pp. 173-174
by Xin Xu, Man-Lap Li
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Understanding the Behavior of Pthread Applications on Non-Uniform Cache ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 175-176
by Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall, Rajeev Balasubramonian
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Exploiting Mutual Awareness between Prefetchers and On-chip Networks in Multi-coresFull-text access may be available. Sign in or learn about subscription options.pp. 177-178
by Junghoon Lee, Minjeong Shin, Hanjoon Kim, John Kim, Jaehyuk Huh
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Decoupled Architectures as a Low-Complexity Alternative to Out-of-order ExecutionFull-text access may be available. Sign in or learn about subscription options.pp. 179-180
by Neal C. Crago, Sanjay J. Patel
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Parameterized Micro-benchmarking: An Auto-tuning Approach for Complex ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 181-182
by Wenjing Ma, Sriram Krishnamoorthy, Gagan Agrawal
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Prediction Based DRAM Row-Buffer Management in the Many-Core EraFull-text access may be available. Sign in or learn about subscription options.pp. 183-184
by Manu Awasthi, David W. Nellans, Rajeev Balasubramonian, Al Davis
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Program InterferometryFull-text access may be available. Sign in or learn about subscription options.pp. 185-186
by Zhe Wang, Daniel A. Jiménez
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Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller EnvironmentsFull-text access may be available. Sign in or learn about subscription options.pp. 187-188
by Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili
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Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 189-190
by Nagendra Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale
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Scalable Proximity-Aware Cache Replication in Chip MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 191-192
by Chongmin Li, Haixia Wang, Yibo Xue, Dongsheng Wang, Jian Li
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Scalable and Efficient Bounds Checking for Large-Scale CMP EnvironmentsFull-text access may be available. Sign in or learn about subscription options.pp. 193-194
by Baik Song An, Ki Hwan Yum, Eun Jung Kim
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An Alternative Memory Access Scheduling in Manycore AcceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 195-196
by Yonggon Kim, Hyunseok Lee, John Kim
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Beforehand Migration on D-NUCA CachesFull-text access may be available. Sign in or learn about subscription options.pp. 197-198
by Javier Lira, Timothy M. Jones, Carlos Molina, Antonio Gonz´lez
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SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 199-200
by Gulay Yalcin, Osman S. Unsal, Adrian Cristal, Ibrahim Hur, Mateo Valero
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rPRAM: Exploring Redundancy Techniques to Improve Lifetime of PCM-based Main MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 201-202
by Jie Chen, Zachary Winter, Guru Venkataramani, H. Howie Huang
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Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 203-204
by Anurag Negi, Per Stenstrom, Rubén Titos-Gil, Manuel E. Acacio, José M. Garcia
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MCFQ: Leveraging Memory-level Parallelism and Application's Cache Friendliness for Efficient Management of Quasi-partitioned Last-level CachesFull-text access may be available. Sign in or learn about subscription options.pp. 205-206
by Dimitris Kaseridis, Muhammad Faisal Iqbal, Jeffrey Stuecheli, Lizy Kurian John
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MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache ReplacementFull-text access may be available. Sign in or learn about subscription options.pp. 207-208
by Ping Zhou, Bo Zhao, Youtao Zhang, Jun Yang, Yiran Chen
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Sampling Temporal Touch Hint (STTH) Inclusive Cache Management PolicyFull-text access may be available. Sign in or learn about subscription options.pp. 209
by Yingying Tian, Daniel A. Jiménez
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Exploiting Rank Idle Time for Scheduling Last-Level Cache WritebackFull-text access may be available. Sign in or learn about subscription options.pp. 210
by Zhe Wang, Daniel A. Jiménez
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TIDeFlow: A Parallel Execution Model for High Performance Computing ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 211
by Daniel Orozco
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Decoupled Cache Segmentation: Mutable Policy with Automated BypassFull-text access may be available. Sign in or learn about subscription options.pp. 212
by Samira Khan, Daniel A. Jiménez
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A Software-Managed Coherent Memory Architecture for ManycoresFull-text access may be available. Sign in or learn about subscription options.pp. 213
by Jungho Park, Choonki Jang, Jaejin Lee
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Improving Last-Level Cache Performance by Exploiting the Concept of MRU-TourFull-text access may be available. Sign in or learn about subscription options.pp. 214
by Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato
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A Compiler-assisted Runtime-prefetching Scheme for Heterogenous PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 215
by Baojiang Shou, Xionghui Hou, Li Chen
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Improving Run-Time Scheduling for General-Purpose Parallel CodeFull-text access may be available. Sign in or learn about subscription options.pp. 216
by Alexandros Tzannes, Rajeev Barua, Uzi Vishkin
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Collaborative Caching for Unknown Cache SizesFull-text access may be available. Sign in or learn about subscription options.pp. 217
by Xiaoming Gu
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Programming Strategies for GPUs and their Power ConsumptionFull-text access may be available. Sign in or learn about subscription options.pp. 218
by Sayan Ghosh, Barbara Chapman
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An Architecture to Enable Lifetime Full Chip Testability in Chip MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 219
by Rance Rodrigues, Israel Koren, Sandip Kundu
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Probabilistic Models Towards Optimal Speculation of DFA ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 220
by Zhijia Zhao, Bo Wu
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STM2: A Parallel STM for High Performance Simultaneous Multithreading SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 221-231
by Gokcen Kestor, Roberto Gioiosa, Tim Harris, Osman S. Unsal, Adrian Cristal, Ibrahim Hur, Mateo Valero
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Making STMs Cache Friendly with Compiler TransformationsFull-text access may be available. Sign in or learn about subscription options.pp. 232-242
by Sandya Mannarswamy, Ramaswamy Govindarajan
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Enhancing Data Locality for Dynamic Simulations through Asynchronous Data Transformations and Adaptive ControlFull-text access may be available. Sign in or learn about subscription options.pp. 243-252
by Bo Wu, Eddy Z. Zhang, Xipeng Shen
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SFMalloc: A Lock-Free and Mostly Synchronization-Free Dynamic Memory Allocator for ManycoresFull-text access may be available. Sign in or learn about subscription options.pp. 253-263
by Sangmin Seo, Junghyun Kim, Jaejin Lee
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Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 264-275
by Meng-Ju Wu, Donald Yeung
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StVEC: A Vector Instruction Extension for High Performance Stencil ComputationFull-text access may be available. Sign in or learn about subscription options.pp. 276-287
by Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan
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OpenMDSP: Extending OpenMP to Program Multi-Core DSPFull-text access may be available. Sign in or learn about subscription options.pp. 288-297
by Jiangzhou He, Wenguang Chen, Guangri Chen, Weimin Zheng, Zhizhong Tang, Handong Ye
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ARIADNE: Agnostic Reconfiguration in a Disconnected Network EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 298-309
by Konstantinos Aisopos, Andrew DeOrio, Li-Shiuan Peh, Valeria Bertacco
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Correctly Treating Synchronizations in Compiling Fine-Grained SPMD-Threaded Programs for CPUFull-text access may be available. Sign in or learn about subscription options.pp. 310-319
by Ziyu Guo, Eddy Zheng Zhang, Xipeng Shen
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Divergence Analysis and OptimizationsFull-text access may be available. Sign in or learn about subscription options.pp. 320-329
by Bruno Coutinho, Diogo Sampaio, Fernando Magno Quintão Pereira, Wagner Meira Jr.
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Large Scale Verification of MPI Programs Using Lamport Clocks with Lazy UpdateFull-text access may be available. Sign in or learn about subscription options.pp. 330-339
by Anh Vo, Ganesh Gopalakrishnan, Robert M. Kirby, Bronis R. de Supinski, Martin Schulz, Greg Bronevetsky
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DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB DirectoryFull-text access may be available. Sign in or learn about subscription options.pp. 340-349
by Carlos Villavieja, Vasileios Karakostas, Lluis Vilanova, Yoav Etsion, Alex Ramirez, Avi Mendelson, Nacho Navarro, Adrian Cristal, Osman S. Unsal
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Linear-time Modeling of Program Working Set in Shared CacheFull-text access may be available. Sign in or learn about subscription options.pp. 350-360
by Xiaoya Xiang, Bin Bao, Chen Ding, Yaoqing Gao
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Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 361-371
by Adrià Armejach, Azam Seyedi, Rubén Titos-Gil, Ibrahim Hur, Adri´n Cristal, Osman S. Unsal, Mateo Valero
An Evaluation of Vectorizing CompilersFull-text access may be available. Sign in or learn about subscription options.pp. 372-382
by Saeed Maleki, Yaoqing Gao, María J. Garzarán, Tommy Wong, David A. Padua
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Modeling and Performance Evaluation of TSO-Preserving Binary OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 383-392
by Cheng Wang, Youfeng Wu
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Exploiting Task Order Information for Optimizing Sequentially Consistent Java ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 393-402
by Christoph M. Angerer, Thomas R. Gross
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Memory Architecture for Integrating Emerging Memory TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 403-412
by Kun Fang, Long Chen, Zhao Zhang, Zhichun Zhu
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Speculative Parallelization in Decoupled Look-aheadFull-text access may be available. Sign in or learn about subscription options.pp. 413-423
by Alok Garg, Raj Parihar, Michael C. Huang
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Optimizing Regular Expression Matching with SR-NFA on Multi-Core SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 424-433
by Yi-Hua E. Yang, Viktor K. Prasanna
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Author IndexFreely available from IEEE.pp. 434-436
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[Publishers information]Freely available from IEEE.pp. 438
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