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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques

Sept. 7 2013 to Sept. 11 2013

Edinburgh, United Kingdom

Table of Contents

CopyrightFreely available from IEEE.pp. ii-ii
General chairs' welcome messageFreely available from IEEE.pp. iii-iii
by Michael O'Boyle, Christian Fensch
INSPIRE: the insieme parallel intermediate representationFreely available from IEEE.pp. 7-18
by Herbert Jordan, Simone Pellegrini, Peter Thoman, Klaus Kofler, Thomas Fahringer
Parallel flow-sensitive pointer analysis by graph-rewritingFreely available from IEEE.pp. 19-28
by Vaivaswatha Nagaraj, R. Govindarajan
Interprocedural strength reduction of critical sections in explicitly-parallel programsFreely available from IEEE.pp. 29-40
by Rajkishore Barik, Jisheng Zhao, Vivek Sarkar
Coordinated power-performance optimization in manycoresFull-text access may be available. Sign in or learn about subscription options.pp. 51-62
by David Kuck, ,
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPsFull-text access may be available. Sign in or learn about subscription options.pp. 63-72
by Calin Cascaval, , ,
APOGEE: adaptive prefetching on GPUs for energy efficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 73-82
by Per Stenstrom, , ,
Parallel frame rendering: trading responsiveness for energy on a mobile GPUFull-text access may be available. Sign in or learn about subscription options.pp. 83-92
by Herbert Jordan, Simone Pellegrini, Peter Thoman, Klaus Kofler, Thomas Fahringer
Exploring hybrid memory for GPU energy efficiency through software-hardware co-designFull-text access may be available. Sign in or learn about subscription options.pp. 93-102
by Vaivaswatha Nagaraj, R. Govindarajan, , , , ,
S-CAVE: effective SSD caching to improve virtual machine storage performanceFull-text access may be available. Sign in or learn about subscription options.pp. 103-112
by Rajkishore Barik, Jisheng Zhao, Vivek Sarkar, , ,
Writeback-aware bandwidth partitioning for multi-core systems with PCMFull-text access may be available. Sign in or learn about subscription options.pp. 113-122
by Filippo Sironi, Martina Maggio, Riccardo Cattaneo, Giovanni F. Del Nero, Donatella Sciuto, Marco D. Santambrogio
L1-bandwidth aware thread allocation in multicore SMT processorsFull-text access may be available. Sign in or learn about subscription options.pp. 123-132
by Hiroshi Sasaki, Satoshi Imamura, Koji Inoue,
A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 133-144
by Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu
Memory-centric system interconnect design with hybrid memory cubesFull-text access may be available. Sign in or learn about subscription options.pp. 145-156
by Ankit Sethia, Ganesh Dasika, Mehrzad Samadi, Scott Mahlke
Neither more nor less: optimizing thread-level parallelism for GPGPUsFull-text access may be available. Sign in or learn about subscription options.pp. 157-166
by Jose-Maria Arnau, Joan-Manuel Parcerisa, Polychronis Xekalakis,
Exploring hybrid memory for GPU energy efficiency through software-hardware co-designFull-text access may be available. Sign in or learn about subscription options.pp. 93-102
by Bin Wang, Bo Wu, Dong Li, Xipeng Shen, Weikuan Yu, Yizheng Jiao, Jeffrey S. Vetter
Fairness-aware scheduling on single-ISA heterogeneous multi-coresFull-text access may be available. Sign in or learn about subscription options.pp. 177-188
by Tian Luo, Siyuan Ma, Rubao Lee, Xiaodong Zhang, Deng Liu, Li Zhou
DANBI: dynamic scheduling of irregular stream programs for many-core systemsFull-text access may be available. Sign in or learn about subscription options.pp. 189-200
by Miao Zhou, Yu Du, Bruce R. Childers, Rami Melhem, Daniel Mosse
An empirical model for predicting cross-core performance interference on multicore processorsFull-text access may be available. Sign in or learn about subscription options.pp. 201-212
by Josue Feliu, Julio Sahuquillo, Salvador Petit, Jose Duato, ,
Jigsaw: scalable software-defined cachesFull-text access may be available. Sign in or learn about subscription options.pp. 213-224
by Sandeep Navada, Niket K. Choudhary, Salil V. Wadhavkar, Eric Rotenberg
Managing shared last-level cache in a heterogeneous multicore processorFull-text access may be available. Sign in or learn about subscription options.pp. 225-234
by Gwangsun Kim, John Kim, Jung Ho Ahn, Jaeha Kim
Reshaping cache misses to improve row-buffer locality in multicore systemsFull-text access may be available. Sign in or learn about subscription options.pp. 235-244
by Onur Kayiran, Adwait Jog, Mahmut T. Kandemir, Chita R. Das
Transparent CPU-GPU collaboration for data-parallel kernels on heterogeneous systemsFull-text access may be available. Sign in or learn about subscription options.pp. 245-256
by Augusto Vega, Alper Buyuktosunoglu, Pradip Bose,
Starchart: hardware and software optimization using recursive partitioning regression treesFull-text access may be available. Sign in or learn about subscription options.pp. 257-268
by Kenzo Van Craeynest, Shoaib Akram, Wim Heirman, Aamer Jaleel, Lieven Eeckhout
RSVM: a region-based software virtual memory for GPUFull-text access may be available. Sign in or learn about subscription options.pp. 269-278
by Changwoo Min, Young Ik Eom,
The case for a scalable coherence protocol for complex on-chip cache hierarchies in many core systemsFull-text access may be available. Sign in or learn about subscription options.pp. 279-288
by Jiacheng Zhao, Xiaobing Feng, Huimin Cui, Youliang Yan, Jingling Xue, Wensen Yang
Meeting midway: improving CMP performance with memory-side prefetchingFull-text access may be available. Sign in or learn about subscription options.pp. 289-298
by Nathan Beckmann, Daniel Sanchez, , , ,
Building expressive, area-efficient coherence directoriesFull-text access may be available. Sign in or learn about subscription options.pp. 299-308
by Vineeth Mekkat, Anup Holey, Pen-Chung Yew, Antonia Zhai,
Traffic steering between a low-latency unswitched TL ring and a high-throughput switched on-chip interconnectFull-text access may be available. Sign in or learn about subscription options.pp. 309-318
by Wei Ding, Jun Liu, Mahmut Kandemir, Mary Jane Irwin
McRouter: multicast within a router for high performance network-on-chipsFull-text access may be available. Sign in or learn about subscription options.pp. 319-330
by Janghaeng Lee, Mehrzad Samadi, Yongjun Park, Scott Mahlke
Concurrent predicates: a debugging technique for every parallel programmerFull-text access may be available. Sign in or learn about subscription options.pp. 331-340
by Wenhao Jia, Kelly A. Shaw, Margaret Martonosi,
Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDGFull-text access may be available. Sign in or learn about subscription options.pp. 341-352
by Feng Ji, Heshan Lin, Xiaosong Ma
Vectorization past dependent branches through speculationFull-text access may be available. Sign in or learn about subscription options.pp. 353-362
by Lucia G. Menezo, Valentin Puente, Jose Angel Gregorio
Automatic vectorization of tree traversalsFull-text access may be available. Sign in or learn about subscription options.pp. 363-374
by Praveen Yedlapalli, Jagadish Kotra, Emre Kultursay, Mahmut Kandemir, Chita R. Das, Anand Sivasubramaniam
Generating efficient data movement code for heterogeneous architectures with distributed-memoryFull-text access may be available. Sign in or learn about subscription options.pp. 375-386
by Lei Fang, Peng Liu, Qi Hu, Michael C. Huang, Guofan Jiang
Automatic OpenCL work-group size selection for multicore CPUsFull-text access may be available. Sign in or learn about subscription options.pp. 387-398
by Jungju Oh, Alenka Zajic, Milos Prvulovic,
McRouter: Multicast within a router for high performance network-on-chipsFull-text access may be available. Sign in or learn about subscription options.pp. 319-329
by Yuan He, Hiroshi Sasaki, Shinobu Miwa, Hiroshi Nakamura
Do inputs matter?: using data-dependence profiling to evaluate thread level speculation in BG/QFull-text access may be available. Sign in or learn about subscription options.pp. 401-402
by Justin Gottschlich, Gilles Pokam, Cristiano Pereira, Youfeng Wu
Can lock-free and combining techniques co-exist?: a novel approach on concurrent queueFull-text access may be available. Sign in or learn about subscription options.pp. 403-404
by Venkatraman Govindaraju, Tony Nowatzki, Karthikeyan Sankaralingam
Task sampling: computer architecture simulation in the many-core eraFull-text access may be available. Sign in or learn about subscription options.pp. 405-406
by Majedul Haque Sujon, R. Clint Whaley, Qing Yi
PS-cache: an energy-efficient cache design for chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 407-408
by Youngjoon Jo, Michael Goldfarb, Milind Kulkarni,
Dynamic memory access monitoring based on tagged memoryFull-text access may be available. Sign in or learn about subscription options.pp. 409-410
by Roshan Dathathri, Chandan Reddy, Thejas Ramashekar, Uday Bondhugula
Exposing ILP in custom hardware with a dataflow compiler IRFull-text access may be available. Sign in or learn about subscription options.pp. 411-412
by Sangmin Seo, Jun Lee, Gangwon Jo, Jaejin Lee
TCPT - Thread criticality-driven prefetcher throttlingFull-text access may be available. Sign in or learn about subscription options.pp. 399-399
by Biswabandan Panda, Shankar Balachandran
Do inputs matter? using data-dependence profiling to evaluate thread level speculation in BG/QFull-text access may be available. Sign in or learn about subscription options.pp. 401-401
by Arnamoy Bhattacharyya
Can lock-free and combining techniques co-exist? A novel approach on concurrent queueFull-text access may be available. Sign in or learn about subscription options.pp. 403-403
by Changwoo Min, Young Ik Eom
Task sampling: Computer architecture simulation in the many-core eraFull-text access may be available. Sign in or learn about subscription options.pp. 405-405
by Thomas Grass
PS-cache: An energy-efficient cache design for chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 407-407
by Joan J. Valls, Alberto Ros, Julio Sahuquillo, Maria E. Gomez
Dynamic memory access monitoring based on tagged memoryFull-text access may be available. Sign in or learn about subscription options.pp. 409-409
by Mikhail Gorelov, Lev Mukhanov
Exposing ILP in custom hardware with a dataflow compiler IRFull-text access may be available. Sign in or learn about subscription options.pp. 411-411
by Ali Mustafa Zaidi
Author indexFreely available from IEEE.pp. 412-412
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