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Reconfigurable Computing and FPGAs, International Conference on

Sept. 28 2005 to Sept. 30 2005

Puebla City, Mexico

ISBN: 0-7695-2456-7

Table of Contents

Introduction
PrefaceFreely available from IEEE.pp. viii
2005 International Conference on Reconfigurable Computing and FPGAs - Title PageFreely available from IEEE.pp. i-iii
2005 International Conference on Reconfigurable Computing and FPGAs - Table of contentsFreely available from IEEE.pp. v-vii
Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scalingFull-text access may be available. Sign in or learn about subscription options.pp. 8 pp.-1
by M.A. Nuno-Maganda, M.O. Arias-Estrada
Cover
2005 International Conference on Reconfigurable Computing and FPGAs - Copyright PageFreely available from IEEE.pp. iv
Introduction
Organizing CommitteeFreely available from IEEE.pp. ix
Introduction
Program CommitteeFreely available from IEEE.pp. x
Session 1: Image Processing
Real-Time FPGA-Based Architecture for Bicubic Interpolation: An Application for Digital Image ScalingFull-text access may be available. Sign in or learn about subscription options.pp. 1
by Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada
Session 1: Image Processing
An Image Comparison Circuit DesignFull-text access may be available. Sign in or learn about subscription options.pp. 2
by Miguel Angel Sánchez Martínez, Adriano De Luca Pennacchia
Session 1: Image Processing
FPGA-Based Customizable Systolic Architecture for Image Processing ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 3
by Griselda Saldaña, Miguel Arias-Estrada
Session 2: Arithmetic
An FPGA Arithmetic Logic Unite for Computing Scalar Multiplication Using the Half-and-Add MethodFull-text access may be available. Sign in or learn about subscription options.pp. 4
by Sabel Mercurio Hernández Rodríguez, Francisco Rodríguez-Henríquez
Session 2: Arithmetic
Hardware Signal Processing Unit for One-Dimensional Variable-Length Discrete Wavelet TransformFull-text access may be available. Sign in or learn about subscription options.pp. 5
by Alejandro Ordaz-Moreno, Rene de Jesus Romero-Troncoso, Jose Alberto Vite-Frias
Session 3: Architecture
A Handel-C Implementation of the Back-Propagation Algorithm on Field Programmable Gate ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 6
by Vijay Pandya, Shawki Areibi, Medhat Moussa
Session 3: Architecture
Rapid Prototyping of a Self-Timed ALU with FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 7
by S. Ortega-Cisneros, J. J. Raygoza-Panduro, J. Suardíaz Muro, E. Boemo
Session 3: Architecture
FPGA Implementation of a Synchronous and Self-Timed NeuroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 8
by J. J. Raygoza-Panduro, S. Ortega-Cisneros, E. Boemo
Session 4: Reconfiguration
On the Design of Two-Level Reconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 9
by Sebastian Lange, Martin Middendorf
Session 4: Reconfiguration
A Secure Self-Reconfiguring Architecture Based on Open-Source HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 10
by Javier Castillo, Pablo Huerta, Victor López, José Ignacio Martínez
Session 4: Reconfiguration
Platform for Intrinsic Evolution of Analogue Neural NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 11
by Patrick Rocke, John Maher, Fearghal Morgan
Session 5: Tools
High Quality Uniform Random Number Generation for Massively Parallel Simulations in FPGASFull-text access may be available. Sign in or learn about subscription options.pp. 12
by David B. Thomas, Wayne Luk
Session 5: Tools
VANNGen: A Flexible CAD Tool for Hardware Implementation of Artificial Neural NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 13
by André L. S. Braga, Carlos H. Llanos, Maurício Ayala-Rincón, Ricardo P. Jacobi
Session 5: Tools
Quartz: A Framework for Correct and Efficient Reconfigurable DesignFull-text access may be available. Sign in or learn about subscription options.pp. 14
by Oliver Pell, Wayne Luk
Session 6: Physical Design
Design Space Exploration of Coarse-Grain Reconfigurable DSPsFull-text access may be available. Sign in or learn about subscription options.pp. 15
by Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek
Session 6: Physical Design
Optimizing Register Binding in FPGAs Using Simulated AnnealingFull-text access may be available. Sign in or learn about subscription options.pp. 16
by Annie Avakian, Iyad Ouaiss
Session 7: Architecture 2
An FPGA Parallel Sorting Architecture for the Burrows Wheeler TransformFull-text access may be available. Sign in or learn about subscription options.pp. 17
by José Martínez, René Cumplido, Claudia Feregrino
Session 8: Tools 2
Dynamic Voting Schemes to Enhance Evolutionary Repair in Reconfigurable Logic DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 18
by Corey J. Milliord, C. A. Sharma, R. F. DeMara
Session 8: Tools 2
Applied VHDL Training Methodology, EDA Framework and Hardware Implementation PlatformFull-text access may be available. Sign in or learn about subscription options.pp. 19
by Fearghal Morgan, Patrick Rocke, Martin O? Halloran
Short Papers
FPGA Implementation of DSVPWM ModulatorFull-text access may be available. Sign in or learn about subscription options.pp. 20
by Ossi Laakkonen, Hannu Sarén, Kimmo Rauma, Olli Pyrhönen
Short Papers
A Novel FPGA Implementation of a Welding Control Using a New Bus ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 21
by K. Rauma, J. Luukko, T. Härkönen, I. Pajari, O. Pyrhönen
Short Papers
On the Design of an FPGA-Based OFDM Modulator for IEEE 802.16-2004Full-text access may be available. Sign in or learn about subscription options.pp. 22
by Joaquín García, René Cumplido
Short Papers
Design and Implementation of an Embedded Microprocessor Compatible with IL Language in Accordance to the Norm IEC 61131-3Full-text access may be available. Sign in or learn about subscription options.pp. 23
by Snaider Carrillo, Agenor Polo, Mario Esmeral
Short Papers
VHDL Core for 1024-Point Radix-4 FFT ComputationFull-text access may be available. Sign in or learn about subscription options.pp. 24
by Jose Alberto Vite-Frias, Rene de Jesus Romero-Troncoso, Alejandro Ordaz-Moreno
Short Papers
Hierarchical FPGA Clustering Based on a Multilevel Partitioning Approach to Improve Routability and Reduce Power DissapationFull-text access may be available. Sign in or learn about subscription options.pp. 25
by Zied Marrakchi, Hayder Mrabet, Habib Mehrez
Short Papers
FPGA Implementation of an Efficient Multiplier over Finite Fields GF(2^m)Full-text access may be available. Sign in or learn about subscription options.pp. 26
by Mario Alberto García-Martínez, Rubén Posada-Gómez, Guillermo Morales-Luna, Francisco Rodríguez-Henríquez
Short Papers
An FPGA-Based Coprocessor for the SPHINX Speech Recognition System: Early ExperiencesFull-text access may be available. Sign in or learn about subscription options.pp. 27
by Guillermo Marcus, Juan A. Nolazco-FIores
Short Papers
Hardware/Software Implementation of a Discrete Cosine Transform Algorithm Using SystemCFull-text access may be available. Sign in or learn about subscription options.pp. 28
by A. Avila, R. Santoyo, S. O. Martinez, G. Dieck
Author Index
Author IndexFreely available from IEEE.pp. 29
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