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Proceedings
RECONFIG
RECONFIG 2010
Generate Citations
Reconfigurable Computing and FPGAs, International Conference on
Dec. 13 2010 to Dec. 15 2010
Cancun, Quintana Roo Mexico
ISBN: 978-0-7695-4314-7
Table of Contents
Papers
Keynote Abstract 2
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pp. xix
Papers
Keynote Abstract 1
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pp. xviii
Papers
Title Page i
Freely available from IEEE.
pp. i
Papers
Title Page iii
Freely available from IEEE.
pp. iii
Papers
[Copyright notice]
Freely available from IEEE.
pp. iv
Papers
Table of contents
Freely available from IEEE.
pp. v-xi
Papers
Message from the Chairs
Freely available from IEEE.
pp. xii
Papers
Organizing Committee
Freely available from IEEE.
pp. xiii
Papers
Program Committee
Freely available from IEEE.
pp. xiv-xvi
Papers
Additional reviewers
Freely available from IEEE.
pp. xvii
Papers
A Minimalistic Architecture for Reconfigurable WFS-Based Immersive-Audio
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pp. 1-6
by
Dimitris Theodoropoulos
,
Georgi Kuzmanov
,
Georgi Gaydadjiev
Papers
MARC: A Many-Core Approach to Reconfigurable Computing
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pp. 7-12
by
Ilia Lebedev
,
Shaoyi Cheng
,
Austin Doupnik
,
James Martin
,
Christopher Fletcher
,
Daniel Burke
,
Mingjie Lin
,
John Wawrzynek
Papers
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space
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pp. 13-18
by
Oliver Sander
,
Benjamin Glas
,
Lars Braun
,
Klaus D. Müller-Glaser
,
Jürgen Becker
Papers
An Efficient Non-blocking Data Cache for Soft Processors
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pp. 19-24
by
Kaveh Aasaraai
,
Andreas Moshovos
Papers
Runtime Task Mapping Based on Hardware Configuration Reuse
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pp. 25-30
by
Kamana Sigdel
,
Carlo Galuzzi
,
Koen Bertels
,
Mark Thompson
,
Andy D. Pimentel
Papers
Modeling and Formal Control of Partial Dynamic Reconfiguration
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pp. 31-36
by
Sébastien Guillet
,
Florent de Lamotte
,
Éric Rutten
,
Guy Gogniat
,
Jean-Philippe Diguet
Papers
Fault Injection Results of Linux Operating on an FPGA Embedded Platform
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pp. 37-42
by
Joshua S. Monson
,
Mike Wirthlin
,
Brad Hutchings
Papers
gNOSIS: A Board-Level Debugging and Verification Tool
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pp. 43-48
by
Ashfaquzzaman Khan
,
Richard Neil Pittman
,
Alessandro Forin
Papers
Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh on FPGAs
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pp. 49-54
by
Jochen Strunk
,
Johannes Hiltscher
,
Wolfgang Rehm
,
Heiko Schick
Papers
Hardware Particle Swarm Optimization Based on the Attractive-Repulsive Scheme for Embedded Applications
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pp. 55-60
by
Daniel M. Muñoz
,
Carlos H. Llanos
,
Leandro dos S. Coelho
,
Mauricio Ayala-Rincón
Papers
FPGA-Based Platform Development for Change Detection in GTAW Welding Process
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pp. 61-66
by
Ronald H. Hurtado
,
Sadek C.A. Alfaro
,
Carlos H. Llanos
Papers
Pruning the Design Space for Just-in-Time Processor Customization
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pp. 67-72
by
Mariusz Grad
,
Christian Plessl
Papers
Applying Model-Checking to Post-Silicon-Verification: Bridging the Specification-Realisation Gap
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pp. 73-78
by
O. Dahmoune
,
R. de B. Johnston
Papers
A Dynamically Reconfigured Network Platform for High-Speed Malware Collection
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pp. 79-84
by
Sascha Mühlbach
,
Andreas Koch
Papers
Design and Implementation of a Visual Fuzzy Control in FPGA for the Ball and Plate System
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pp. 85-90
by
Marco A. Moreno-Armendáriz
,
Elsa Rubio
,
César A. Pérez-Olvera
Papers
Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures
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pp. 91-96
by
J. Angermeier
,
S. Wildermann
,
E. Sibirko
,
J. Teich
Papers
An Application Example of a Run-Time Reconfigurable Embedded System
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pp. 97-102
by
Daniel Kriesten
,
Volker Pankalla
,
Ulrich Heinkel
Papers
Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations
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pp. 103-108
by
Mingjie Lin
,
Shaoyi Cheng
,
John Wawrzynek
Papers
UCORE: Reconfigurable Platform for Educational Purposes
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pp. 109-114
by
Francisco J. Quiles
,
Manuel Ortiz
,
Maria Brox
,
Carlos D. Moreno
,
Javier Hormigo
,
Julio Villalba
Papers
A Two Level Architecture for High Throughput DCT-Processor and Implementing on FPGA
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pp. 115-120
by
Azad Fakhari
,
Mahmood Fathy
Papers
Parallel FPGA-Based Implementation of Recursive Sorting Algorithms
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pp. 121-126
by
Dmitri Mihhailov
,
Valery Sklyarov
,
Iouliia Skliarova
,
Alexander Sudnitson
Papers
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart
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pp. 127-131
by
Rui A.L. de Cristo
,
Ricardo P. Jasinski
,
Volnei A. Pedroni
Papers
Reconfigurable Digital Audio Mixer for Electroacoustic Music
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pp. 132-137
by
David Pedrosa Branco
,
Iouliia Skliarova
,
José Vieira
Papers
A Hardware Architecture of an XML/XPath Broker for Content-Based Publish/Subscribe Systems
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pp. 138-143
by
Fadi El-Hassan
,
Dan Ionescu
Papers
A Runtime Profiler: Toward Virtualization of Polymorphic Computing Platforms
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pp. 144-149
by
Hamid Mushtaq
,
Mojtaba Sabeghi
,
Koen Bertels
Papers
Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM)
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pp. 150-155
by
Luís Vitório Cargnini
,
Yoann Guillemenet
,
Lionel Torres
,
Gilles Sassatelli
Papers
A Novel Hardware Implementation of the Compact Genetic Algorithm
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pp. 156-161
by
Marco A. Moreno-Armendáriz
,
Nareli Cruz-Cortés
,
Alejandro Léon-Javier
Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture
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pp. 162-167
by
Shady O. Agwa
,
Hany H. Ahmad
,
Awad I. Saleh
Papers
Multi-channel Driving Systems for Therapeutic Applications Based-on Focused Ultrasound
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pp. 168-172
by
J. Pindter-Medina
,
S. Pichardo
,
L. Curiel
,
A.D. Garcia-Garcia
,
J.E. Chong-Quero
Papers
Reconfigurable Node Processing Unit for a Low-Power Wireless Sensor Network
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pp. 173-178
by
Luis A. Vera-Salas
,
Sandra V. Moreno-Tapia
,
Roque A. Osornio-Rios
,
Rene de_J. Romero-Troncoso
Papers
Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware
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pp. 179-184
by
Bruno A. Silva
,
Mauricio A. Dias
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Jorge L. Silva
,
Fernando S. Osorio
Papers
FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System
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pp. 185-189
by
Khaled Sobaihi
,
Akram Hammoudeh
,
David Scammell
Papers
A New Hardware Efficient Inversion Based Random Number Generator for Non-uniform Distributions
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pp. 190-195
by
Christian de Schryver
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Daniel Schmidt
,
Norbert Wehn
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Elke Korn
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Henning Marxen
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Ralf Korn
Papers
Performance Analysis of Hardware/Software Middleware in Network of Smart Camera Systems
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pp. 196-201
by
Ali Akbar Zarezadeh
,
Christophe Bobda
Papers
Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations
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pp. 202-207
by
Xiang Tian
,
Khaled Benkrid
Papers
Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGA
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pp. 208-213
by
Wendi Wang
,
Bo Duan
,
Chunming Zhang
,
Peiheng Zhang
,
Ninghui Sun
Papers
Parallel Data Sort Using Networked FPGAs
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pp. 214-219
by
Janardhan Singaraju
,
John A. Chandy
Papers
Issues on Building an MPI Cluster on Microblaze
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pp. 220-225
by
Juan-Carlos Díaz-Martín
,
Carolina Gómez-Tostón Gutiérrez
,
Álvaro Cortés Fácila
,
Juan-Antonio Rico-Gallego
Papers
Modeling and Simulation of Reconfigurable Processors in Grid Networks
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pp. 226-231
by
M. Faisal Nadeem
,
Mahmood Ahmadi
,
M. Nadeem
,
Stephan Wong
Papers
Accelerating Texture Features Extraction Algorithms Using FPGA Architecture
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pp. 232-237
by
Ali Reza Akoushideh
,
Asadollah Shahbahrami
Papers
Huffman Coding-Based Compression Unit for Embedded Systems
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pp. 238-243
by
Marco Antonio Soto Hernández
,
Oscar Alvarado-Nava
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Francisco Javier Zaragoza Martínez
Papers
FPGA-Based Online Detection of Multiple-Combined Faults through Information Entropy and Neural Networks
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pp. 244-249
by
Eduardo Cabal-Yepez
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Ricardo Saucedo-Gallaga
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Armando G. Garcia-Ramirez
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Arturo A. Fernandez-Jaramillo
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Marcos Pena-Anaya
,
Martin Valtierra-Rodriguez
Papers
Reconfigurable Cache Implemented on an FPGA
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pp. 250-255
by
A.D. Santana Gil
,
J.I. Benavides Benitez
,
M. Hernandez Calviño
,
E. Herruzo Gómez
Papers
Hardware Computation of the PageRank Eigenvector
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pp. 256-261
by
Séamas McGettrick
,
Dermot Geraghty
Papers
Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAs
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pp. 262-267
by
Crina Costea
,
Florent Bernard
,
Viktor Fischer
,
Robert Fouquet
Papers
Cross-Correlation Cartography
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pp. 268-273
by
Laurent Sauvage
,
Sylvain Guilley
,
Florent Flament
,
Jean-Luc Danger
,
Yves Mathieu
Papers
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs
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pp. 274-279
by
Shaunak Shah
,
Rajesh Velegalati
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Jens-Peter Kaps
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David Hwang
Papers
HCrypt: A Novel Concept of Crypto-processor with Secured Key Management
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pp. 280-285
by
Lubos Gaspar
,
Viktor Fischer
,
Florent Bernard
,
Lilian Bossuet
,
Pascal Cotret
Papers
High-Speed FPGA-Based Pseudorandom Generators with Extremely Long Periods
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pp. 286-291
by
Mieczyslaw Jessa
,
Michal Jaworski
Papers
Skein Tree Hashing on FPGA
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pp. 292-297
by
Aric Schorr
,
Marcin Lukowiak
Papers
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs
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pp. 298-303
by
Yohei Hori
,
Takahiro Yoshida
,
Toshihiro Katashita
,
Akashi Satoh
Papers
Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results
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pp. 304-309
by
Julien Francq
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Céline Thuillet
Papers
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA
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pp. 310-315
by
Zouha Cherif
,
Florent Flament
,
Jean-Luc Danger
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Shivam Bhasin
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Sylvain Guilley
,
Hervé Chabanne
On FPGA-Based Implementations of the SHA-3 Candidate Grøstl
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pp. 316-321
by
Bernhard Jungk
,
Steffen Reith
Papers
An Improved GF(2) Matrix Inverter with Linear Time Complexity
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pp. 322-327
by
Ricardo P. Jasinski
,
Volnei A. Pedroni
,
Antonio Gortan
,
Walter Godoy Jr.
Papers
Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface
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pp. 328-333
by
Christoforos Kachris
,
George Nikiforos
,
Stamatis Kavadias
,
Vassilis Papaefstathiou
,
Manolis Katevenis
Papers
Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip
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pp. 334-339
by
Andrew G. Schmidt
,
William V. Kritikos
,
Erik K. Anderson
,
Ron Sass
,
Matthew French
Papers
A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks
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pp. 340-345
by
Angelo Kuti Lusala
,
Jean-Didier Legat
Papers
A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC
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pp. 346-351
by
Nicolas Hébert
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Gabriel Marchesan Almeida
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Pascal Benoit
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Gilles Sassatelli
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Lionel Torres
Papers
Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis
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pp. 352-357
by
Cristinel Ababei
Papers
Operating System Structures for Multiprocessor Systems on Programmable Chip
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pp. 358-363
by
Miaoqing Huang
,
David Andrews
,
Jason Agron
Papers
Low Power Dual Core Microcontroller
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pp. 364-369
by
Rajesh Kannan Megalingam
,
Ashwin Mohan
,
Shekhil Hassan Thavalengal
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Tanmay Muralidhar Rao
,
Vivek Periye
Papers
A Process-Oriented Streaming System Design Paradigm for FPGAs
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pp. 370-375
by
Ling Liu
,
Oleksii Morozov
Papers
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip
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pp. 376-381
by
Ludovic Devaux
,
Sebastien Pillement
,
Daniel Chillet
,
Didier Demigny
Papers
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism
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pp. 382-387
by
Gabriel Marchesan Almeida
,
Sameer Varyani
,
Rémi Busseuil
,
Nicolas Hebert
,
Gilles Sassatelli
,
Pascal Benoit
,
Lionel Torres
,
Michel Robert
Papers
Power Consumption Calculation of AP-DCD Algorithm Using FPGA Platform
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pp. 388-393
by
Sasmita Deo
Papers
Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform
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pp. 394-399
by
Mohamed El-Hadedy
,
Martin Margala
,
Danilo Gligoroski
,
Svein J. Knapskog
Papers
Singular Value Decomposition Hardware for MIMO: State of the Art and Custom Design
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pp. 400-405
by
Yue Wang
,
Kevin Cunningham
,
Prawat Nagvajara
,
Jeremy Johnson
Papers
FPGA Implementation of Adjustable Wideband Fractional Delay FIR Filters
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pp. 406-411
by
G. Ramirez-Conejo
,
J. Diaz-Carmona
,
A. Ramirez-Agundis
,
A. Padilla-Medina
,
J. Delgado-Frias
Papers
A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition Stage in GPS
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pp. 412-417
by
E. Romero-Aguirre
,
R. Parra-Michel
,
O. Longoria-Gandara
,
M. Aguirre-Hernández
Papers
Using Partial Reconfiguration in an Embedded Message-Passing System
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pp. 418-423
by
Manuel Saldaña
,
Arun Patel
,
Hao Jun Liu
,
Paul Chow
Papers
Run-Time Reconfiguration for Automatic Hardware/Software Partitioning
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pp. 424-429
by
Tom Davidson
,
Karel Bruneel
,
Dirk Stroobandt
Papers
Configuration Sharing Optimized Placment and Routing
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pp. 430-435
by
Piotr Stepien
,
John Cobb
Papers
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules
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pp. 436-441
by
Valery Sklyarov
,
Iouliia Skliarova
,
Dmitri Mihhailov
,
Alexander Sudnitson
Papers
An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels
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pp. 442-447
by
Michael Schmidt
,
Dietmar Fey
Papers
Open Source Precision Timed Soft Processor for Cyber Physical System Applications
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pp. 448-451
by
Stephen Craven
,
Daniel Long
,
Jason Smith
Papers
Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution
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pp. 452-457
by
Holger Flatt
,
Holger Blume
,
Peter Pirsch
Papers
Flex-SURF: A Flexible Architecture for FPGA-Based Robust Feature Extraction for Optical Tracking Systems
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pp. 458-463
by
Michael Schaeferling
,
Gundolf Kiefer
Papers
Author Index
Freely available from IEEE.
pp. 464-467
Papers
[Publisher information]
Freely available from IEEE.
pp. 468
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