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Reconfigurable Computing and FPGAs, International Conference on

Nov. 30 2011 to Dec. 2 2011

Cancun, Quintana Roo Mexico

ISBN: 978-0-7695-4551-6

Table of Contents

Papers
Title Page iFreely available from IEEE.pp. i
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Title Page iiiFreely available from IEEE.pp. iii
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[Copyright notice]Freely available from IEEE.pp. iv
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Table of contentsFreely available from IEEE.pp. v-xii
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Message from ChairsFreely available from IEEE.pp. xiii
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Organizing CommitteeFreely available from IEEE.pp. xiv
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Program CommitteeFreely available from IEEE.pp. xv-xviii
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Additional ReviewersFreely available from IEEE.pp. xix
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KeynotesFreely available from IEEE.pp. xx-xxii
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An Analysis of Implanted Antennas in Xilinx FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Jacob Couch, Peter Athanas
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Adaptive Multi-client Network-on-Chip MemoryFull-text access may be available. Sign in or learn about subscription options.pp. 7-12
by Diana Göehringer, Lukas Meder, Michael Hübner, Jürgen Becker
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FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point DividersFull-text access may be available. Sign in or learn about subscription options.pp. 13-19
by Malte Baesler, Sven-Ole Voigt, Thomas Teufel
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Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input PermutationsFull-text access may be available. Sign in or learn about subscription options.pp. 20-26
by Ameer Abdelhadi, Guy G.F. Lemieux
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Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault OcurrenceFull-text access may be available. Sign in or learn about subscription options.pp. 27-34
by Xabier Iturbe, Khaled Benkrid, Tughrul Arslan, Chuan Hong, Imanol Martinez
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Resource Efficient Arithmetic Effects on RBM Neural Network Solution Quality Using MNISTFull-text access may be available. Sign in or learn about subscription options.pp. 35-40
by Antony W. Savich, Medhat Moussa
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Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window DecompositionFull-text access may be available. Sign in or learn about subscription options.pp. 41-48
by Jeffrey B. Goeders, Guy G.F. Lemieux, Steven J.E. Wilton
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Object Recognition on a Chip: A Complete SURF-Based System on a Single FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 49-54
by Michael Schaeferling, Gundolf Kiefer
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Measuring and Predicting Temperature Distributions on FPGAs at Run-TimeFull-text access may be available. Sign in or learn about subscription options.pp. 55-60
by Markus Happe, Andreas Agne, Christian Plessl
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Heterogeneous Concurrent Error Detection (hCED) Based on Output AnticipationFull-text access may be available. Sign in or learn about subscription options.pp. 61-66
by Naveed Imran, Ronald F. Demara
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Configuring Field-Programmable Robot ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 67-73
by Mark G. Arnold
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Identifying Merge-Beneficial Software Kernels for Hardware ImplementationFull-text access may be available. Sign in or learn about subscription options.pp. 74-79
by Adriano Sanches, João M.P. Cardoso, Alexandre C.B. Delbem
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A Reconfigurable Computing System Based on a Cache-Coherent FabricFull-text access may be available. Sign in or learn about subscription options.pp. 80-85
by Neal Oliver, Rahul R. Sharma, Stephen Chang, Bhushan Chitlur, Elkin Garcia, Joseph Grecco, Aaron Grier, Nelson Ijih, Yaping Liu, Pratik Marolia, Henry Mitchel, Suchit Subhaschandra, Arthur Sheiman, Tim Whisonant, Prabhat Gupta
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Multi-stream Regular Expression Matching on FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 86-91
by Qu Yun, Yi-Hua E. Yang, Viktor K. Prasanna
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Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based ThermometersFull-text access may be available. Sign in or learn about subscription options.pp. 92-98
by Moinuddin A. Sayed, Phillip H. Jones
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Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 99-104
by Rizwan A. Ashraf, Ouns Mouri, Rami Jadaa, Ronald F. Demara
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An Architecture for Reconfigurable Multi-core ExplorationsFull-text access may be available. Sign in or learn about subscription options.pp. 105-110
by Olivier Serres, Vikram K. Narayana, Tarek El-Ghazawi
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Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 111-116
by Hui Zhu, Sébastien Le Beux, Nataliya Yakymets, Ian O'Connor
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Hardware OS Communication Service and Dynamic Memory Management for RSoCsFull-text access may be available. Sign in or learn about subscription options.pp. 117-122
by Surya Narayanan, Daniel Chillet, Sebastien Pillement, Ioannis Sourdis
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Dynamic Processor ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 123-128
by M. Hübner, C. Tradowsky, D. Göhringer, L. Braun, F. Thoma, J. Henkel, J. Becker
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GIMME - A General Image Multiview Manipulation EngineFull-text access may be available. Sign in or learn about subscription options.pp. 129-134
by Carl Ahlberg, Jörgen Lidholm, Fredrik Ekstrand, Giacomo Spampinato, Mikael Ekström, Lars Asplund
Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 135-140
by Thomas Schweizer, Philipp Schlicker, Sven Eisenhardt, Tommy Kuhn, Wolfgang Rosenstiel
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A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 141-145
by Drausio Linardi Rossi, Vanderlei Bonato, Eduardo Marques, João Miguel Gago Pontes de Brito Lima
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FPGA Based Acceleration of Decimal OperationsFull-text access may be available. Sign in or learn about subscription options.pp. 146-151
by Alberto Nannarelli
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MiniMIPS: An 8-Bit MIPS in an FPGA for Educational PurposesFull-text access may be available. Sign in or learn about subscription options.pp. 152-157
by Cesar Ortega-Sanchez
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Linking Formal Description and Simulation of Runtime Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 158-163
by Thilo Pionteck, Christoph Osterloh, Carsten Albrecht
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 164-169
by Ruben Salvador, Andres Otero, Javier Mora, Eduardo de la Torre, Lukas Sekanina, Teresa Riesgo
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Optimizing Decomposition-Based Packet Classification Implementation on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 170-175
by Lu Sun, Hoang Le, Viktor K. Prasanna
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Dynamic Constant Reconfiguration for Explicit Finite Difference Option PricingFull-text access may be available. Sign in or learn about subscription options.pp. 176-181
by Tobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston
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Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable ComputingFull-text access may be available. Sign in or learn about subscription options.pp. 182-189
by Xabier Iturbe, Khaled Benkrid, Ali Ebrahim, Chuan Hong, Tughrul Arslan, Imanol Martinez
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A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in BioinformaticsFull-text access may be available. Sign in or learn about subscription options.pp. 190-197
by Pei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul
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An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic UnitsFull-text access may be available. Sign in or learn about subscription options.pp. 198-203
by Suvarna Mane, Lyndon Judge, Patrick Schaumont
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MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processorFull-text access may be available. Sign in or learn about subscription options.pp. 204-210
by Michal Varchola, Tim Guneysu, Oliver Mischke
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dcTPM: A Generic Architecture for Dynamic Context ManagementFull-text access may be available. Sign in or learn about subscription options.pp. 211-216
by Thomas Feller, Sunil Malipatlolla, Michael Kasper, Sorin A. Huss
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA ImplementationsFull-text access may be available. Sign in or learn about subscription options.pp. 217-222
by Wei He, Eduardo de la Torre, Teresa Riesgo
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Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable FunctionFull-text access may be available. Sign in or learn about subscription options.pp. 223-228
by Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh
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Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear PairingsFull-text access may be available. Sign in or learn about subscription options.pp. 229-234
by Cuautémoc Ch´vez Corona, Edgar Ferrer Moreno, Francisco Rodríguez Henríquez
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Area-Efficient FPGA Implementations of the SHA-3 FinalistsFull-text access may be available. Sign in or learn about subscription options.pp. 235-241
by Bernhard Jungk, Jürgen Apfelbeck
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Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 242-248
by Ahmad Salman, Marcin Rogawski, Jens-Peter Kaps
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Decrypting HDCP-protected Video Streams Using Reconfigurable HardwareFull-text access may be available. Sign in or learn about subscription options.pp. 249-254
by Benno Lomb, Tim Güneysu
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Robustness Analysis of Different AES Implementations on SRAM Based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 255-260
by Uli Kretzschmar, Armando Astarloa, Jesús L´zaro, Unai Bidarte, Jaime Jiménez
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Efficient Dual-Rail Implementations in FPGA Using Block RAMsFull-text access may be available. Sign in or learn about subscription options.pp. 261-267
by Shivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger
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Versatile FPGA Architecture for Skein Hashing AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 268-273
by David M. Webster, Marcin Lukowiak
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Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling MethodFull-text access may be available. Sign in or learn about subscription options.pp. 274-279
by Mieczyslaw Jessa, Lukasz Matuszewski
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RAM-Based Ultra-Lightweight FPGA Implementation of PRESENTFull-text access may be available. Sign in or learn about subscription options.pp. 280-285
by Elif Bilge Kavun, Tolga Yalcin
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A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic ReconfigurabilityFull-text access may be available. Sign in or learn about subscription options.pp. 286-290
by Marcus R. Perrett, Izzat Darwazeh
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FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual InformationFull-text access may be available. Sign in or learn about subscription options.pp. 291-296
by Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Jose Juan Garcia-Hernandez
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Improving KLT in Embedded Systems by Processing Oversampling Video Sequence in Real-TimeFull-text access may be available. Sign in or learn about subscription options.pp. 297-302
by Zhilei Chai, Jianbo Shi
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Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel EstimationFull-text access may be available. Sign in or learn about subscription options.pp. 303-308
by E. Romero-Aguirre, R. Parra-Michel, Roberto Carrasco-Alvarez, A.G. Orozco-Lugo
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Adaptive Energy-Efficient Architecture for WCDMA Channel EstimationFull-text access may be available. Sign in or learn about subscription options.pp. 309-314
by Zoltan E. Rakosi, Zheng Wang, Anupam Chattopadhyay
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High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel EmulationFull-text access may be available. Sign in or learn about subscription options.pp. 315-320
by L.R. Vela-Garcia, J. Vazquez Castillo, R. Parra-Michel, A. Castillo Atoche
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Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 321-326
by Pedro Cervantes-Lozano, Luis F. Gonz´lez-Pérez, Andrés D. García-García
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Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 327-332
by Dongdong Chen, Mihai Sima
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Design and Implementation of a Simplified Turbo Decoder for 3GPP2Full-text access may be available. Sign in or learn about subscription options.pp. 333-338
by Lennin C. Yllescas-Calderón, Adrian J. Espino-Orozco, R. Parra-Michel, Luis F. Gonz´lez-Pérez
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Arbitrary Distribution Random Variable Generator for Channel EmulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 339-344
by R. Zarate-Martínez, F. Peña-Campos, J. Vazquez Castillo, R. Parra-Michel
Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n MatricesFull-text access may be available. Sign in or learn about subscription options.pp. 345-350
by Luis M. Ledesma-Carrillo, Eduardo Cabal-Yepez, Rene de J. Romero-Troncoso, Arturo Garcia-Perez, Roque A. Osornio-Rios, Tobia D. Carozzi
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Reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 351-356
by J. Aylward, C.H. Crawford, K. Inoue, S. Lekuch, K. Muller, M. Nutter, H. Penner, K. Schleupen, J. Xenidis
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Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space ExplorationFull-text access may be available. Sign in or learn about subscription options.pp. 357-362
by Remi Busseuil, Lyonel Barthe, Gabriel Marchesan Almeida, Luciano Ost, Florent Bruguier, Gilles Sassatelli, Pascal Benoit, Michel Robert, Lionel Torres
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Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 363-368
by Hamed S. Kia, Cristinel Ababei
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The Impact of Global Routing on the Performance of NoCs in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 369-374
by Ye Lu, John Mccanny, Sakir Sezer
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Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable CoreFull-text access may be available. Sign in or learn about subscription options.pp. 375-379
by J.C. Peña-Ramos, R. Parra-Michel
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FPGA Bootstrapping on PCIe Using Partial ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 380-385
by Patrick S. Ostler, Michael J. Wirthlin, Joshua E. Jensen
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From Instruction Traces to Specialized Reconfigurable ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 386-391
by João Bispo, Nuno Paulino, João M.P. Cardoso, João Canas Ferreira
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Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 392-397
by Srinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Pérez-Andrade
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A Self-Configuring TMR Scheme Utilizing Discrepancy ResolutionFull-text access may be available. Sign in or learn about subscription options.pp. 398-403
by Naveed Imran, Ronald F. Demara
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Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual VthFull-text access may be available. Sign in or learn about subscription options.pp. 404-409
by Kazuei Hironaka, Hideharu Amano
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Scalable Models for Autonomous Self-Assembled Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 410-415
by T. Cervero, S. Lopez, R. Sarmiento, T. Frangieh, P. Athanas
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Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 416-421
by Krzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada
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Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring InfrastructureFull-text access may be available. Sign in or learn about subscription options.pp. 422-427
by Andrew G. Schmidt, Ron Sass
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Low-Power Reconfigurable Component Utilization in a High-Level Synthesis FlowFull-text access may be available. Sign in or learn about subscription options.pp. 428-433
by Dimitris Bekiaris, George Economakos, Efstathios Sotiriou-Xanthopoulos, Dimitrios Soudris
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RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive ComputersFull-text access may be available. Sign in or learn about subscription options.pp. 434-441
by Benjamin Thielmann, Thorsten Wink, Jens Huthmann, Andreas Koch
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LiSARD: LabVIEW Integrated Softcore Architecture for Reconfigurable DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 442-447
by A. Pacholik, J. Klöckner, M. Müller, I. Gushchina, W. Fengler
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EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 448-454
by Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
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Automatic Type Inference for Resynthesis on Hardware Description LanguagesFull-text access may be available. Sign in or learn about subscription options.pp. 455-461
by Germ´n León, Germ´n Fabregat, José M. Claver
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Enumeration of Costas Arrays Using GPUs and FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 462-467
by Rafael A. Arce-Nazario, Jose R. Ortiz-Ubarri
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An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston ModelFull-text access may be available. Sign in or learn about subscription options.pp. 468-474
by Christian de Schryver, Ivan Shcherbakov, Frank Kienle, Norbert Wehn, Henning Marxen, Anton Kostiuk, Ralf Korn
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Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUsFull-text access may be available. Sign in or learn about subscription options.pp. 475-480
by Hanaa M. Hussain, Khaled Benkrid, Ahmet T. Erdogan, Huseyin Seker
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GPU vs FPGA: Example Application on White Light InterferometryFull-text access may be available. Sign in or learn about subscription options.pp. 481-486
by A. Pacholik, M. Müller, W. Fengler, T. Machleidt, K.-H. Franke
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Spectral Method Characterization on FPGA and GPU AcceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 487-492
by Karl Pereira, Peter Athanas, Heshan Lin, Wu Feng
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Digital Talking Book Player for the Visually Impaired Using FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 493-496
by Azadeh Nazemi, Cesar Ortega-Sanchez, Iain Murray
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Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing ApplicationFull-text access may be available. Sign in or learn about subscription options.pp. 497-500
by L.A. Cardona, J. Agrawal, Y. Guo, J. Oliver, C. Ferrer
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Toward All Optical Interconnections in Chip Multiprocessor (2)Full-text access may be available. Sign in or learn about subscription options.pp. 501-504
by M. Channoufi, P. Lecoy, R. Attia, B. Delacressonniere, S. Garcia
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Techniques for Dynamically Mapping Computations to CoprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 505-508
by João Bispo, João M.P. Cardoso
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Reconfigurable Block Floating Point Processing Elements in Virtex PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 509-512
by Guillermo Conde, Gregory W. Donohoe
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Author IndexFreely available from IEEE.pp. 513-516
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[Publishers information]Freely available from IEEE.pp. 518
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