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Rapid System Prototyping, IEEE International Workshop on

June 21 2000 to June 23 2000

Paris, France

ISSN: 1074-6005

ISBN: 0-7695-0668-2

Table of Contents

IntroductionFreely available from IEEE.pp. viii
Chairmen's MessageFreely available from IEEE.pp. ix
AcknowledgementsFreely available from IEEE.pp. x
Session 1: Co-Design Methodologies
A Methodology for Implementing Medium Access Protocols Using a General Parameterized ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 2
Session 1: Co-Design Methodologies
Design Space Exploration for Hardware/Software Codesign of Multiprocessor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 8
Session 1: Co-Design Methodologies
Efficient Modeling of Preemption in a Virtual PrototypeFull-text access may be available. Sign in or learn about subscription options.pp. 14
Session 1: Co-Design Methodologies
Combining Virtual Benchmarking with Rapid System Prototyping for Real-Time Embedded Multiprocessor Signal Processing System CodesignFull-text access may be available. Sign in or learn about subscription options.pp. 20
Session 2: Software Methodologies
A Risk Assessment Model for Software Prototyping ProjectsFull-text access may be available. Sign in or learn about subscription options.pp. 28
Session 2: Software Methodologies
Processor Models for Retargetable ToolsFull-text access may be available. Sign in or learn about subscription options.pp. 34
Session 2: Software Methodologies
MODUS: Integrated Behavior-Oriented Model for Rapid PrototypingFull-text access may be available. Sign in or learn about subscription options.pp. 40
Session 2: Software Methodologies
Equivalence Checking of Two Statechart SpecificationsFull-text access may be available. Sign in or learn about subscription options.pp. 46
Session 2: Software Methodologies
Intuitive Design of Complex Real-Time Control SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 52
Session 3: Tools
Cycle-True Simulation of the ST10 Microcontroller Including the Core and the PeripheralsFull-text access may be available. Sign in or learn about subscription options.pp. 60
Power-constrained block-test list schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 182-187
Session 3: Tools
Hardware/Software Co-Design of a Java Virtual MachineFull-text access may be available. Sign in or learn about subscription options.pp. 66
Session 3: Tools
Emulator Environment Based on an FPGA Prototyping BoardFull-text access may be available. Sign in or learn about subscription options.pp. 72
Session 3: Tools
A Comprehensive Prototyping-Platform for Hardware-Software CodesignFull-text access may be available. Sign in or learn about subscription options.pp. 78
Session 4: Real Time Systems
Quasi-Static Scheduling of Reconfigurable Dataflow Graphs for DSP SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 84
Session 4: Real Time Systems
A Design Methodology for Hardware Prototyping of Integrated AC Drive Control: Application to Direct Torque Control of an Induction MachineFull-text access may be available. Sign in or learn about subscription options.pp. 90
Session 5: Hardware Methodologies
Speeding Up Hardware Prototyping by Incremental Simulation/EmulationFull-text access may be available. Sign in or learn about subscription options.pp. 98
Session 5: Hardware Methodologies
Mapping a High-Speed Wireless Communication Function to the Reconfigurable J-PlatformFull-text access may be available. Sign in or learn about subscription options.pp. 103
Session 5: Hardware Methodologies
A Prototype of an AAL for High Bit Rate Real-Time Data Transmission System over ATM Networks Using a RSE CODECFull-text access may be available. Sign in or learn about subscription options.pp. 109
Session 5: Hardware Methodologies
The FLYSIG Prototyping ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 115
Session 6: Code Generation
A Verilog to C CompilerFull-text access may be available. Sign in or learn about subscription options.pp. 122
Session 6: Code Generation
Using MetaScribe to Prototype an UML to C++/Ada95 Code GeneratorFull-text access may be available. Sign in or learn about subscription options.pp. 128
Session 6: Code Generation
An Evaluation of Code Generation Strategies Targeting Hardware for the Rapid Prototyping of SDL-SpecificationsFull-text access may be available. Sign in or learn about subscription options.pp. 134
Session 7: Methodologies
Integration and Evolution of Model-Based Tool PrototypesFull-text access may be available. Sign in or learn about subscription options.pp. 142
Session 7: Methodologies
Coprocessor Synthesis of Multirate System Using Static Scheduling TheoryFull-text access may be available. Sign in or learn about subscription options.pp. 148
Session 7: Methodologies
Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded SystemFull-text access may be available. Sign in or learn about subscription options.pp. 154
Session 7: Methodologies
Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 160
Session 8: Reconfigurability in Hardware Systems
Reconfigurable Instruction Set Processors: A SurveyFull-text access may be available. Sign in or learn about subscription options.pp. 168
Session 8: Reconfigurability in Hardware Systems
Highly Configurable Control Boards: A Tool and a Design ExperienceFull-text access may be available. Sign in or learn about subscription options.pp. 174
Session 9: Hardware Systems
Power-Constrained Block-Test List SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 182
Session 9: Hardware Systems
Adaptive FPGA Placement by Natural OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 188
Session 9: Hardware Systems
A Hardware Virtual Machine for the Networked ReconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 194
Session 9: Hardware Systems
FPGA Technology Snapshot: Current Devices and Design ToolsFull-text access may be available. Sign in or learn about subscription options.pp. 200
Session 11: Methodologies
Validation of Link Layer Synthesizable Core - A Prototyping Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 208
Session 11: Methodologies
Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data StreamsFull-text access may be available. Sign in or learn about subscription options.pp. 214
Session 12: Embedded Systems
Efficient Clock-Cycle Precise Simulation at Architecture Level in C++Full-text access may be available. Sign in or learn about subscription options.pp. 222
Session 12: Embedded Systems
Embedded System Architecture Design Based on Real-Time EmulationFull-text access may be available. Sign in or learn about subscription options.pp. 228
Session 12: Embedded Systems
Author IndexFreely available from IEEE.pp. 234
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