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Proceedings
VLSID
VLSID 2015
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2015 28th International Conference on VLSI Design (VLSID)
Jan. 3 2015 to Jan. 7 2015
Bangalore, India
Table of Contents
Title Page i
Freely available from IEEE.
pp. i-i
Title Page iii
Freely available from IEEE.
pp. iii-iii
Copyright Page
Freely available from IEEE.
pp. iv-iv
Table of Contents
Freely available from IEEE.
pp. v-xiii
Message from the General Co-Chairs
Freely available from IEEE.
pp. xv-xv
Message from the Technical Program Co-Chairs
Freely available from IEEE.
pp. xvi-xvi
Message from the Organizing Co-Chairs
Freely available from IEEE.
pp. xvii-xvii
Message from the Steering Committee Chair
Freely available from IEEE.
pp. xviii-xviii
Message from the President, VLSI Society of India
Freely available from IEEE.
pp. xix-xix
About the Cover from the Publication Chair
Freely available from IEEE.
pp. xx-xx
by
A. Garimella
VLSI Design Conference Steering Committee (2014)
Freely available from IEEE.
pp. xxi-xxi
VLSI Design 2015 Conference Committee
Freely available from IEEE.
pp. xxii-xxv
Technical Program Committee
Freely available from IEEE.
pp. xxvi-xxix
VLSI Design Conference history
Freely available from IEEE.
pp. xxx-xxx
Embedded Systems Design Conference History
Freely available from IEEE.
pp. xxxi-xxxi
VLSID 2015 -- List of Technical Co-Sponsors
Freely available from IEEE.
pp. xxxii-xxxii
Call for Papers -- VDAT 2015
Freely available from IEEE.
pp. xxxiii-xxxiii
Tutorial T1: Neuromorphic Computing - Algorithms, Devices and Systems
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pp. 1-2
by
Bipin Rajendran
,
Udayan Ganguly
,
Manan Suri
Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems
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pp. 3-5
by
Prabhat Mishra
,
Swarup Bhunia
,
Srivaths Ravi
Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control
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pp. 6-7
by
J.A. Abraham
,
A. Chatterjee
Tutorial T4: MEMS: Design, Fabrication, and their Applications as Chemical and Biosensors
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pp. 8-9
by
Nitin S. Kale
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test
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pp. 10-11
by
Nagesh Tamarapalli
,
Prashanth Vallur
,
Sachin Sudhakar Kulkarni
Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges
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pp. 12-13
by
S. Dasgupta
,
B. Anand
Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of Things
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pp. 14-15
by
Debdeep Mukhopadhyay
,
Rajat Subhra Chakraborty
,
Phuong Ha Nguyen
,
Durga Prasad Sahoo
Tutorial T8: Scheduling Issues in Embedded Real-Time Systems
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pp. 16-16
by
Parmesh Ramanathan
Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCs
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pp. 17-18
by
Sriram Ganesan
Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs
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pp. 19-20
by
Adit D. Singh
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement
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pp. 21-23
by
Wu-Tung Cheng
,
Sudhakar M. Reddy
Special session: Continuous-flow biochips: Current platforms and emerging research challenges
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pp. 24-27
by
Paul Pop
,
Tsung-Yi Ho
,
Krishnendu Chakrabarty
,
William H. Grover
Invited Talk: IoT Protocols War and the Way Forward
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pp. 28-28
by
Virendra Gupta
,
Jayaraghavendran
ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA
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pp. 29-34
by
Jude Angelo Ambrose
,
Tuo Li
,
Daniel Murphy
,
Shivam Gargg
,
Nick Higgins
,
Sri Parameswaran
Parameterizable FPGA Framework for Particle Filter Based Object Tracking in Video
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pp. 35-40
by
Pinalkumar Engineer
,
Rajbabu Velmurugan
,
Sachin Patkar
RELSPEC: A Framework for Early Reliability Refinement of Embedded Applications
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pp. 41-46
by
Saurav Kumar Ghosh
,
Aritra Hazra
,
Soumyajit Dey
Thermal Extension of the Total Bandwidth Server
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pp. 47-52
by
Rehan Ahmed
,
Ayoosh Bansal
,
Bhuvana Kakunoori
,
Parameswaran Ramanathan
,
Kewal K. Saluja
Thermal-Aware Test Data Compression Using Dictionary Based Coding
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pp. 53-58
by
Rajit Karmakar
,
Santanu Chattopadhyay
CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip
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pp. 59-64
by
Rimpy Bishnoi
,
Vijay Laxmi
,
Manoj Singh Gaur
,
Radi Husin Bin Ramlee
,
Mark Zwolinski
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors
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pp. 65-70
by
Neethu Bal Mallya
,
Geeta Patil
,
Biju Raveendran
A Frequency Scan Scheme for PLL-Based Locking to High-Q MEMS Resonators
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pp. 71-74
by
Anjan Kumar
,
Abhinav Dikshit
,
Bill Clark
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Jeff Yan
NFC for Pervasive Healthcare Monitoring
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pp. 75-80
by
T.V. Prabhakar
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Ujwal Mysore
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Uday Saini
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K.J. Vinoy
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Bharadwaj Amruthur
Hardware Solution for Real-Time Face Recognition
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pp. 81-86
by
Gopinath Mahale
,
Hamsika Mahale
,
Arnav Goel
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S.K. Nandy
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S. Bhattacharya
,
Ranjani Narayan
Towards a Real-Time Campus-Scale Water Balance Monitoring System
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pp. 87-92
by
Vignesh D. Kudva
,
Prashanth Nayak
,
Alok Rawat
,
G.R. Anjana
,
K.R. Sheetal Kumar
,
Bharadwaj Amrutur
,
M.S. Mohan Kumar
Robot Navigation Using Neuro-electronic Hybrid Systems
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pp. 93-98
by
Jude Baby George
,
Grace Mathew Abraham
,
Bharadwaj Amrutur
,
Sujit Kumar Sikdar
Comparison of Off-Chip Training Methods for Neuromemristive Systems
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pp. 99-104
by
Cory Merkel
,
Dhireesha Kudithipudi
OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip
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pp. 105-110
by
Ramon Fernandes
,
Lucas Brahm
,
Thais Webber
,
Rodrigo Cataldo
,
Leticia B. Poehls
,
Cesar Marcon
Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip
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pp. 111-116
by
Dharanidhar Dang
,
Biplab Patra
,
Rabi Mahapatra
,
Martin Fiers
A Hardware and Thermal Analysis of DVFS in a Multi-core System with Hybrid WNoC Architecture
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pp. 117-122
by
Sri Harsha Gade
,
Hemanta Kumar Mondal
,
Sujay Deb
Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing
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pp. 123-128
by
Matthew Kennedy
,
Avinash Karanth Kodi
Effects of Nondeterminism in Hardware and Software Simulation with Thread Mapping
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pp. 129-134
by
Giordano Salvador
,
Siddharth Nilakantan
,
Baris Taskin
,
Mark Hempstead
,
Ankit More
Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation
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pp. 135-140
by
Siddharth Nilakantan
,
Scott Lerner
,
Mark Hempstead
,
Baris Taskin
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs
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pp. 141-146
by
Shirshendu Das
,
Hemangee K. Kapoor
Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations
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pp. 147-152
by
Santanu Sarma
,
Nikil Dutt
Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations
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pp. 153-158
by
Farhad Merchant
,
Arka Maity
,
Mahesh Mahadurkar
,
Kapil Vatwani
,
Ishan Munje
,
Madhava Krishna
,
S. Nalesh
,
Nandhini Gopalan
,
Soumyendu Raha
,
S.K. Nandy
,
Ranjani Narayan
On-the-Fly Donut Formation in Compiled Memory
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pp. 159-163
by
Darvinder Singh
,
Isha Garg
,
Vineet Sachan
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Prasanna Nalawar
Scaling the UVM_REG Model towards Automation and Simplicity of Use
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pp. 164-169
by
Abhishek Jain
,
Richa Gupta
On the Analysis of Reversible Booth's Multiplier
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pp. 170-175
by
Jakia Sultana
,
Sajib Kumar Mitra
,
Ahsan Raja Chowdhury
Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs
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pp. 176-180
by
M. Sultan
,
M. Siddiqui
,
Shailendra Sharad
,
Yogendra Sharma
,
Amit Khanuja
A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM
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pp. 181-185
by
Kedar Janardan Dhori
,
Vinay Kumar
,
Ashish Kumar
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids
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pp. 186-191
by
Nitin Salodkar
,
Subramanian Rajagopalan
,
Sambuddha Bhattacharya
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Shabbir Batterywala
Formal Methods for Pattern Based Reliability Analysis in Embedded Systems
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pp. 192-197
by
Sumana Ghosh
,
Pallab Dasgupta
On Event Driven Modeling of Continuous Time Systems
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pp. 198-203
by
Dushyant Juneja
A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface
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pp. 204-208
by
Vinod Inipodu Murugan
,
Narayanan Mayandi
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Sendhil Arul
A Design Approach for Compressor Based Approximate Multipliers
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pp. 209-214
by
Naman Maheshwari
,
Zhixi Yang
,
Jie Han
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Fabrizio Lombardi
Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging
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pp. 215-220
by
Chandrashekar Dusa
,
Samiyuktha Kalalii
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P. Rajalakshmi
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Omkeshwar Rao
Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures
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pp. 221-226
by
Karthik Swaminathan
,
Jagadish Kotra
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Huichu Liu
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Jack Sampson
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Mahmut Kandemir
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Vijaykrishnan Narayanan
Exploring Scope of Power Reduction with Constrained Physical Synthesis
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pp. 227-231
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Kaustav Guha
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Sourav Saha
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Ricardo Nigaglioni
All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters
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pp. 232-237
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Pratik Dutta
,
Chandan Bandyopadhyay
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Hafizur Rahaman
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming
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pp. 238-243
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Nusrat Jahan Lisa
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Hafiz Md. Hasan Babu
On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback
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pp. 244-248
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K.S. Rakshitdatta
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Nagendra Krishnapura
Accurate Constant Transconductance Generation without Off-Chip Components
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pp. 249-253
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Imon Mondal
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Nagendra Krishnapura
Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI
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pp. 254-259
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Saurabh Kumar Singh
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Gautam Dey Kanungo
Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOS
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pp. 260-264
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Saurabh Kumar Singh
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Nitin Bansal
A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application
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pp. 265-270
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T. Rahul
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Bibhudatta Sahoo
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Veeresh Babu Vulligaddala
A Wide Tuning Range LC Quadrature Phase Oscillator Employing Mode Switching
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pp. 271-275
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Sivaramakrishna Rudrapati
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Sharayu Jagtap
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Md. Umar Shaikh
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Shalabh Gupta
Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life
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pp. 276-281
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Radhika Gupta
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Atul Bhargava
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Rakeshshenoy Panemangalore
Recessed MOSFET in 28 nm FDSOI for Better Breakdown Characteristics
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pp. 282-285
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N.K. Kranthi
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Radhakrishnan Sithanandam
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Rama Komaragiri
A Noise Aware CML Latch Modelling for Large System Simulation
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pp. 286-291
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Debesh Bhatta
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Suvadeep Bannerjee
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Abhijit Chatterjee
Design of High Speed Ternary Full Adder and Three-Input XOR Circuits Using CNTFETs
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pp. 292-297
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Sneh Lata Murotiya
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Anu Gupta
An Efficient Transition Detector Exploiting Charge Sharing
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pp. 298-303
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Yu Wang
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Adit D. Singh
A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications
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pp. 304-309
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Unsuk Heo
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Xueqing Li
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Sumeet Gupta
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Suman Datta
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Vijaykrishnan Narayanan
Power Optimization Techniques for DDR3 SDRAM
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pp. 310-315
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Preeti Ranjan Panda
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Vishal Patel
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Praxal Shah
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Namita Sharma
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Vaidyanathan Srinivasan
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Dipankar Sarma
A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic
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pp. 316-320
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S. Dinesh Kumar
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Noor Mahammad Sk
Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
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pp. 321-326
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Guilherme Heck
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Leandro S. Heck
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Ajay Singhvi
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Matheus T. Moreira
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Peter A. Beerel
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Ney L. V. Calazans
Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters
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pp. 327-332
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Pramod Kumar Meher
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Basant Kumar Mohanty
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M.M.S. Swamy
SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques
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pp. 333-338
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Ankur Jaiswal
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Bharat Garg
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Vikas Kaushal
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An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications
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pp. 339-344
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J.G. Pandey
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A. Karmakar
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C. Shekhar
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FPGA Based Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration
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pp. 345-350
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Gayathri R. Prabhu
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Bibin Johnson
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J. Sheeba Rani
A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications
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pp. 351-356
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Sunil Dutt
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Anshu Chauhan
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Energy Aware Computation Driven Approximate DCT Architecture for Image Processing
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pp. 357-362
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Vikas Kaushal
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Bharat Garg
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Ankur Jaiswal
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New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation
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pp. 363-368
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V.R. Devanathan
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Lakshmanan Balasubramanian
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Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis
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pp. 369-374
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Hadi Hajimiri
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Kamran Rahmani
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DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs
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Pradeep Nair
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Nagarajan Viswanathan
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation
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pp. 381-386
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V.R. Devanathan
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Diagnostic Tests for Pre-bond TSV Defects
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Bei Zhang
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Vishwani D. Agrawal
Few Good Frequencies for Power-Constrained Test
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pp. 393-398
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Sindhu Gunasekar
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Vishwani D. Agrawal
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits
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pp. 399-404
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Xijiang Lin
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Sudhakar M. Reddy
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Janusz Rajski
Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs
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pp. 405-410
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F. Lavratti
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L. M. Bolzani Poehls
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Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance
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pp. 411-416
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Gaurav Narang
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Pragya Sharma
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Mansi Jain
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A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement
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Shankar Balachandran
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Monitoring AMS Simulation: From Assertions to Features
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pp. 429-434
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Antara Ain
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Pallab Dasgupta
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