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Proceedings 18th IEEE VLSI Test Symposium

Apr. 30 2000 to May 4 2000

Montreal, Canada

ISSN: 1093-0167

ISBN: 0-7695-0613-5

Table of Contents

ForewordFreely available from IEEE.pp. xiii
Organizing CommitteeFreely available from IEEE.pp. xv
Steering CommitteeFreely available from IEEE.pp. xvii
Program CommitteeFreely available from IEEE.pp. xix
ReviewersFreely available from IEEE.pp. xxvii
VTS '99 Best Paper AwardFreely available from IEEE.pp. xxii
VTS '99 Best Panel AwardFreely available from IEEE.pp. xxiii
Test Technology Technical CouncilFull-text access may be available. Sign in or learn about subscription options.pp. xxv
Test Technology Educational Program: Overview of TutorialsFreely available from IEEE.pp. xxxi
Plenary Session
Keynote Address: Optical Internet: Industry ChallengesFreely available from IEEE.pp. xxxvii
Session 1: Microprocessor Test/Validation
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 3
by Nandu Tendolkar, Robert Molyneaux, Carol Pyron, Rajesh Raina, Inc. Motorola
Session 1: Microprocessor Test/Validation
Validation of PowerPC(tm) Custom Memories using Symbolic SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 9
by Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
Session 1: Microprocessor Test/Validation
On Testing the Path Delay Faults of a Microprocessor Using its Instruction SetFull-text access may be available. Sign in or learn about subscription options.pp. 15
by Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
Session 2: Low Power BIST and Scan
Low Power/Energy BIST Scheme for DatapathsFull-text access may be available. Sign in or learn about subscription options.pp. 23
by D. Gizopoulos, N. Kranitis, M. Psarakis, A Paschalis, Y. Zorian
Session 2: Low Power BIST and Scan
Low Power BIST via Non-Linear Hybrid Cellular AutomataFull-text access may be available. Sign in or learn about subscription options.pp. 29
by Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante
Session 2: Low Power BIST and Scan
Static Compaction Techniques to Control Scan Vector Power DissipationFull-text access may be available. Sign in or learn about subscription options.pp. 35
by Ranganathan Sankaralingam, Rama Rao Oruganti, Nur A. Touba
Session 3: Technology Trends and Their Impact on Test
Silicon-on-Insulator Technology Impacts on SRAM TestingFull-text access may be available. Sign in or learn about subscription options.pp. 43
by R. Dean Adams, Phil Shephard Iii
Session 3: Technology Trends and Their Impact on Test
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process VariationFull-text access may be available. Sign in or learn about subscription options.pp. 49
by Byungwoo Choi, D.M.H. Walker
Session 3: Technology Trends and Their Impact on Test
Self-Checking Circuits versus Realistic Faults in Very Deep SubmicronFull-text access may be available. Sign in or learn about subscription options.pp. 55
by Lorena Anghel, Michael Nicolaidis, Issam Alzaher-Noufal
Session 4: Scan Related Approaches
BSM2: Next Generation Boundary-Scan MasterFull-text access may be available. Sign in or learn about subscription options.pp. 67
by Frank P. Higgins, Rajagopalan Srinivasan
Session 4: Scan Related Approaches
Virtual Scan Chains: A Means for Reducing Scan Length in CoresFull-text access may be available. Sign in or learn about subscription options.pp. 73
by Abhijit Jas, Bahram Pouya, Nur A. Touba
Session 4: Scan Related Approaches
A Rapid and Scalable Diagnosis Scheme for BIST Environments with a Large Number of Scan ChainsFull-text access may be available. Sign in or learn about subscription options.pp. 79
by Jayabrata Ghosh-Dastidar, Nur A. Touba
Session 5: Defect Driven Techniques
A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 89
by Hugo Cheung, Sandeep K. Gupta
Session 5: Defect Driven Techniques
Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 97
by Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee
Session 5: Defect Driven Techniques
PROBE: A PPSFP Simulator for Resistive Bridging FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 105
by Chul Young Lee, D.M.H. Walker
Session 6: System-on-chip Test Techniques
Test Data Compression for System-on-a-Chip Using Golomb CodesFull-text access may be available. Sign in or learn about subscription options.pp. 113
by Anshuman Chandra, Krishnendu Chakrabarty
Session 6: System-on-chip Test Techniques
Test and Debug of Networking SoCs: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 121
by A. Bommireddy, J. Khare, S. Shaikh, S-T. Su
Session 6: System-on-chip Test Techniques
Design of System-on-a-Chip Test Access Architectures using Integer Linear ProgrammingFull-text access may be available. Sign in or learn about subscription options.pp. 127
by Krishnendu Chakrabarty
Session 7: Analog Test Techniques
Test Generation for Accurate Prediction of Analog SpecificationsFull-text access may be available. Sign in or learn about subscription options.pp. 137
by Ram Voorakaranam, Abhijit Chatterjee
Session 7: Analog Test Techniques
A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based TestFull-text access may be available. Sign in or learn about subscription options.pp. 143
by Jeongjin Roh, Jacob A. Abraham
Session 7: Analog Test Techniques
Test Selection Based on High Level Fault Simulation for Mixed-Signal SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 149
by Sule Ozev, Alex Orailoglu
Session 8: BIST: Arithmetic, Memories and ILAs
Integrating Logic BIST in VLSI Designs with Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 157
by Vivek Chickermane, Scott Richter, Carl Barnhart
Session 8: BIST: Arithmetic, Memories and ILAs
Synthesis for Arithmetic Built-In Self-TestFull-text access may be available. Sign in or learn about subscription options.pp. 165
by Albrecht P. Stroele
Session 8: BIST: Arithmetic, Memories and ILAs
General BIST-Amenable Method of Test Generation for Iterative Logic ArraysFull-text access may be available. Sign in or learn about subscription options.pp. 171
by Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu
SPECIAL SESSION 2: Embedded Tutorial
RF/Analog Test of Circuits and SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 179
by M.S. Huetmaker
Session 9: Temperature and Process Drift Issues
Cold Delay Defect ScreeningFull-text access may be available. Sign in or learn about subscription options.pp. 183
by Chao-Wen Tseng, Edward J. McCluskey, Xiaoping Shao, David M. Wu
The left edge algorithm and the tree growing technique in block-test scheduling under power constraintsFull-text access may be available. Sign in or learn about subscription options.pp. 417-422
by Valentin Muresan, X. Wang, Valentina Muresan, M. Vladutiu
Session 9: Temperature and Process Drift Issues
Thermal Testing: Fault Location StrategiesFull-text access may be available. Sign in or learn about subscription options.pp. 189
by J. Altet, A. Rubio, E. Schaub, S. Dialhaire, W. Claeys
Session 9: Temperature and Process Drift Issues
Detection of CMOS Defects under Variable Processing ConditionsFull-text access may be available. Sign in or learn about subscription options.pp. 195
by Amy Germida, James Plusquellic
Session 10: Test Compaction and Design Validation
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault RestorationFull-text access may be available. Sign in or learn about subscription options.pp. 205
by Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
Session 10: Test Compaction and Design Validation
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 213
by Markus Seuring, Krishnendu Chakrabarty
Session 10: Test Compaction and Design Validation
ESIM: A Multimodel Design Error and Fault Simulator for Logic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 221
by Hussain Al-Asaad, John P. Hayes
Session 11: Analog BIST
An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked LoopsFull-text access may be available. Sign in or learn about subscription options.pp. 231
by Seongwon Kim, Mani Soma, Dilip Risbud
Session 11: Analog BIST
Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-TestFull-text access may be available. Sign in or learn about subscription options.pp. 237
by Jan Arild Tofte, Chee-Kian Ong, Jiun-Lang Huang, Kwang-Ting (Tim) Cheng
Session 11: Analog BIST
Hardware Resource Minimization for Histogram-Based ADC BISTFull-text access may be available. Sign in or learn about subscription options.pp. 247
by M. Renovell, F. Azaïs, S. Bernard, Y. Bertrand
Session 12: Functional Test and Verification Issues
DEFUSE: A Deterministic Functional Self-Test Methodology for ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 255
by Li Chen, Sujit Dey
Session 12: Functional Test and Verification Issues
Testing, Verification, and Diagnosis in the Presence of UnknownsFull-text access may be available. Sign in or learn about subscription options.pp. 263
by A. Jain, V. Boppana, R. Mukherjee, J. Jain, M. ~Fujita, M. Hsiao
Session 12: Functional Test and Verification Issues
Using Arithmetic Transform for Verification of Datapath Circuits via Error ModelingFull-text access may be available. Sign in or learn about subscription options.pp. 271
by Katarzyna Radecka, Zeljko Zilic
Session 13: Memory Test
Functional Memory Faults: A Formal Notation and a TaxonomyFull-text access may be available. Sign in or learn about subscription options.pp. 281
by Ad J. van de Goor, Zaid Al-Ars
Session 13: Memory Test
Simulation-Based Test Algorithm Generation for Random Access MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 291
by Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu
Session 13: Memory Test
Detection of Inter-Port Faults in Multi-Port Static RAMsFull-text access may be available. Sign in or learn about subscription options.pp. 297
by J. Zhao, S. Irrinki, M. Puri, F. Lombardi
Session 14: Open Defect Detection, Diagnosis and Analog BIST
Detectability Conditions for Interconnection Open DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 305
by Victor H. Champac, Antonio Zenteno
Session 14: Open Defect Detection, Diagnosis and Analog BIST
A Technique for Logic Fault Diagnosis of Interconnect Open DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 313
by Srikanth Venkataraman, Scott B. Drummonds
Session 14: Open Defect Detection, Diagnosis and Analog BIST
Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter ApproximationsFull-text access may be available. Sign in or learn about subscription options.pp. 319
by José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski
SPECIAL SESSION 3: Open Projector
How Should Fault Coverage Be Defined?Full-text access may be available. Sign in or learn about subscription options.pp. 325
by T.W. Williams, S. Sunter
SPECIAL SESSION 5: Panel
Biomedical ICs: What is Different about Testing those ICs?Full-text access may be available. Sign in or learn about subscription options.pp. 329
by B. Vinnakota, Andre Ivanov
Session 15: Delay Test, Diagnosis and BIST
Bounding Circuit Delay by Testing a Very Small Subset of PathsFull-text access may be available. Sign in or learn about subscription options.pp. 333
by Manish Sharma, Janak H. Patel
Session 15: Delay Test, Diagnosis and BIST
On Test Set Generation for Efficient Path Delay Fault DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 343
by Ramesh C. Tekumalla
Session 15: Delay Test, Diagnosis and BIST
A Low-Speed BIST Framework for High-Performance Circuit TestingFull-text access may be available. Sign in or learn about subscription options.pp. 349
by H.G. Kerkhoff, M. Shashaani, M. Sachdev
Session 16: BIST Issues
Hidden Markov and Independence Models with Patterns for Sequential BISTFull-text access may be available. Sign in or learn about subscription options.pp. 359
by Laurent Brehelin, Olivier Gascuel, Gilles Caraux, Patrick Girard, Christian Landrault
Session 16: BIST Issues
Reducing Test Application Time for Built-in-Self-Test Test Pattern GeneratorsFull-text access may be available. Sign in or learn about subscription options.pp. 369
by Ilker Hamzaoglu, Janak H. Patel
Session 16: BIST Issues
Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern GeneratorsFull-text access may be available. Sign in or learn about subscription options.pp. 377
by Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
Session 17: STIL Extension, Jitter, and Crosstalk
P1450.1: STIL for the Simulation EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 389
by Peter Wohl, Nathan Biggs
Session 17: STIL Extension, Jitter, and Crosstalk
Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal MethodFull-text access may be available. Sign in or learn about subscription options.pp. 395
by Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, Toshifumi Watanabe, Tadahiro Ohmi[4]
Session 17: STIL Extension, Jitter, and Crosstalk
Crosstalk Effect Removal for Analog Measurement in Analog Test BusFull-text access may be available. Sign in or learn about subscription options.pp. 403
by Chauchin Su, Yue-Tsang Chen
Session 18: High Level ATPG and Test Scheduling
High-Level Observability for Effective High-Level ATPGFull-text access may be available. Sign in or learn about subscription options.pp. 411
by Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero
Session 18: High Level ATPG and Test Scheduling
The Left Edge Algorithm and the Tree Growing Technique in Block-Test Scheduling under Power ConstraintsFull-text access may be available. Sign in or learn about subscription options.pp. 417
by Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu
Session 18: High Level ATPG and Test Scheduling
Testability Alternatives Exploration through Functional TestingFull-text access may be available. Sign in or learn about subscription options.pp. 423
by F. Ferrandi, G. Fornara, D. Sciuto, G. Ferrara, F. Fummi
Session 19: IDDQ Test
Efficient Diagnosis of Single/Double Bridging Faults with Delta Iddq Probabilistic Signatures and Viterbi AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 431
by C. Thibeault
Session 19: IDDQ Test
Delta Iddq for Testing ReliabilityFull-text access may be available. Sign in or learn about subscription options.pp. 439
by Theo J. Powell, James Pair, Melissa St. John, Doug Counce
Session 19: IDDQ Test
Clustering Based Evaluation of IDDQ Measurements: Applications in Testing and Classification of ICsFull-text access may be available. Sign in or learn about subscription options.pp. 444
by Sri Jandhyala, Hari Balachandran, Manidip Sengupta, Anura P. Jayasumana
Session 20: On-line Testing and Fault Tolerance
Fault Escapes in Duplex SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 453
by Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
Session 20: On-line Testing and Fault Tolerance
Invariance-Based On-Line Test for RTL Controller-Datapath CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 459
by Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu
Session 20: On-line Testing and Fault Tolerance
Word Voter: A New Voter Design for Triple Modular Redundant SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 465
by Subhasish Mitra, Edward J. McCluskey
SPECIAL SESSION 7: Panel
Do I Need this Tool for My Chips to Work?Full-text access may be available. Sign in or learn about subscription options.pp. 471
by F. Muradali, A. Ivanov
SPECIAL SESSION 8: Panel
High End and Low End Applications for Defective Chips: Enhanced Availability and AcceptabilityFull-text access may be available. Sign in or learn about subscription options.pp. 473
by M. Breuer
SPECIAL SESSION 8: Panel
Author IndexFreely available from IEEE.pp. 475
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