Bus Encoding Technique Using Forbidden Transition Free Algorithm for Cross-Talk Reduction for On-chip VLSI Interconnect

In this work, we propose a bus encoding technique using a variety of binary Fibonacci representation to reduce crosstalk delay and give a recursive procedure to generate crosstalk delay free binary Fibonacci code words. Based on the idea, we proposed a coding technique by considering a variant of binary Fibonacci representation. Here we use a variant of binary Fibonacci representation by considering the Fibonacci number {F1, F2, F3, F4…} as the basis elements of binary Fibonacci number system. By considering F1 as one of the basis elements of the binary Fibonacci number system, we can eliminate the possibility of simultaneous opposite transaction on adjacent lines, thus crosstalk delay can be prevented. We use the notation Fm to represent the set of m-bit crosstalk delay free binary Fibonacci code words where the weight of ith bit is the value of ith Fibonacci number i.e. Fi, 1 ≤ i ≤ m, in the sequence {1,1,2,3,5}. Now here our mapping and coding scheme is based on the Fibonacci number system and the mathematical analysis shows that all numbers can be represented by forbidden transition free (FTF) vectors in the Fibonacci numeral system (FSN). Crosstalk induced delay and power consumption have become a major determinant of the system performances. Reducing crosstalk can greatly boost the system performance. So the design is highly efficient, modular and can be easily combined with a bus partitioning technique.