Analysis of a multiple bus multiprocessor

C.-H. Tung; C.W. McCarron

doi:10.1109/ACSSC.1992.269085

Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers

Analysis of a multiple bus multiprocessor

Year: 1992, Pages: 925,926,927,928,929

DOI Bookmark: 10.1109/ACSSC.1992.269085

Authors

C.-H. Tung, Dept. of Comput. Sci. & Eng., Connecticut Univ., Storrs, CT, USA
C.W. McCarron, Dept. of Comput. Sci. & Eng., Connecticut Univ., Storrs, CT, USA

Abstract

A multiple-bus architecture capable of supporting a large number of processors is analyzed. The bandwidth of this architecture is studied. The results of a trace-driven simulation used to investigate the performance of the system are given. The performance advantage of the architecture is demonstrated.<>

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Analysis of a multiple bus multiprocessor

Authors

Abstract

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