Design of a real time image compression system using multiple DSP 56000/96000 processors

S. Srinivasan; E.C. Monie; G.V.K. Prasad

doi:10.1109/ACSSC.1993.342338

Proceedings of 27th Asilomar Conference on Signals, Systems and Computers

Design of a real time image compression system using multiple DSP 56000/96000 processors

Year: 1993, Pages: 1632,1633,1634,1635

DOI Bookmark: 10.1109/ACSSC.1993.342338

Authors

S. Srinivasan, Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India
E.C. Monie, Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India
G.V.K. Prasad, Dept. of Electr. Eng., Indian Inst. of Technol., Madras, India

Abstract

An image compression system has been implemented using DSP 56000/96000 family of processors. Block processing is done on image data of 8/spl times/8 size to reduce I/O overheads. The coding scheme uses Discrete Cosine Transform (DCT) followed by a Llyod-Max quantizer. A multiprocessor system using these processors has also been designed for compression of 512/spl times/512 images in real time.<>

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Design of a real time image compression system using multiple DSP 56000/96000 processors

Authors

Abstract

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