Abstract
A fault tolerant pipelined architecture for high sampling rate adaptive filters is presented. The architecture, which is based on the computational requirements of delayed LMS and adaptive lattice filters, offers robust performance in the presence of single hardware faults, and software faults resulting from numerical instability. The reliability of the proposed system is analyzed and compared to the existing implementations strategies, and methods for fault detection, fault location, and recovery via hardware reconfiguration are discussed. Finally, simulation results illustrating recovery from processor fault are presented.<>