Abstract
The strategies for breaking a cipher has been shifting towards side channel attacks which exploit the run-time physical attributes of cryptographic chips. Among the many such attacks, the scan-based attack has become a convenient approach for attackers to extract the secret information. As reported in academic research, the scan-based side-channel attacks have been successfully mounted on Advanced Encryption Standard (AES) crypto chips. On the other hand, the scan design-for-test (DfT) has become a mandatory practice for almost all the modern designs for the test, debug, and diagnosis. Therefore, the development of a secure scan test technique is very much needed, which can effectively countermeasure the scan attacks on cryptographic chips. In this paper, we propose a new countermeasure against scan attacks on AES crypto chips. The proposed countermeasure is based on the principle of test response encryption. The scan chain content can be scanned out only in encrypted form and hence cannot be analysed by an unauthorised user. The proposed countermeasure thwarts all the known scan attacks on scan design without compromising on its test capabilities. Moreover, the extra circuitry used for test response encryption is used during mission mode to achieve 2X throughput compared with the conventional iterative AES architecture.