Abstract
The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using different delay models such as unit delay, fanout delay, and random delay in power estimation of XOR dominated logic. Due to different possible implementations of XOR gate, we model the XOR gate as a basic gate and a complex static CMOS gate, respectively. Power dissipation due to (charging and discharging) internal node capacitances is also considered.