Concept and Extraction Method of ESD-Critical Parameters for Function-Based Layout-Level ESD Protection Circuit Design Verification

R. Y. Zhan; H. G. Feng; Q. Wu; X. K. Guan; G. Chen; H. L. Xie; A. Z. Wang

doi:10.1109/ASPDAC.2004.73

Asia and South Pacific Design Automation Conference

Concept and Extraction Method of ESD-Critical Parameters for Function-Based Layout-Level ESD Protection Circuit Design Verification

Year: 2004, Pages: 710-712

DOI Bookmark: 10.1109/ASPDAC.2004.73

Authors

R. Y. Zhan, Illinois Institute of Technology, Chicago, IL
H. G. Feng, Illinois Institute of Technology, Chicago, IL
Q. Wu, Illinois Institute of Technology, Chicago, IL
X. K. Guan, Illinois Institute of Technology, Chicago, IL
G. Chen, Illinois Institute of Technology, Chicago, IL
H. L. Xie, Illinois Institute of Technology, Chicago, IL
A. Z. Wang, Illinois Institute of Technology, Chicago, IL

Abstract

On-chip ESD (electrostatic discharging) protection is a challenging IC design problem. New CAD tools are essential to ESD protection design prediction and verification at full chip level. This paper reports a novel concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification, which has been used to develop the first intelligent CAD tool of such kind. Design examples in 0.35μm BiCMOS are presented.

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Concept and Extraction Method of ESD-Critical Parameters for Function-Based Layout-Level ESD Protection Circuit Design Verification

Authors

Abstract

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