A new multiport memory for high performance parallel processor system with shared memory

K. Hirano; T. Ono; H. Kurino; M. Koyanagi

doi:10.1109/ASPDAC.1998.669491

Proceedings of 1998 Asia and South Pacific Design Automation Conference

A new multiport memory for high performance parallel processor system with shared memory

Year: 1998, Pages: 333,334

DOI Bookmark: 10.1109/ASPDAC.1998.669491

Authors

K. Hirano, Graduate Sch. of Eng., Tohoku Univ., Sendai, Japan
T. Ono
H. Kurino
M. Koyanagi

Abstract

We describe a new multiport memory which is called Shared DRAM (SHDRAM) to solve bus-bottle neck problem in parallel processor system with shared memory. This SHDRAM has four ports. Therefore four processors can be directly connected to this memory without bus-bottle neck. The basic operation of SHDRAM is confirmed by computer simulation and measurement results.

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A new multiport memory for high performance parallel processor system with shared memory

Authors

Abstract

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