An efficient solution to the storage correspondence problem for large sequential circuits

Traditional state-traversal-based methods for verifying sequential circuits are computationally infeasible for circuits with a large number of memory elements. However, if the correspondence of the memory elements of the two circuits can be established, a difficult sequential verification problem can be transformed into an easier combinational verification problem. In this paper, we propose an approach that combines two complementary simulation-based methods for fast and accurate storage correspondence. Experiments on the large ISCAS89 benchmark circuits demonstrate the superiority.