Proceedings of the Ninth Asian Test Symposium
Reducing test application time for full scan circuits by the addition of transfer sequences
DOI Bookmark: 10.1109/ATS.2000.893643
Authors
I. Pomeranz, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USAS.M. Reddy, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA