Reducing test application time for full scan circuits by the addition of transfer sequences

I. Pomeranz; S.M. Reddy

doi:10.1109/ATS.2000.893643

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Proceedings of the Ninth Asian Test Symposium

Reducing test application time for full scan circuits by the addition of transfer sequences

Year: 2000, Pages: 317

DOI Bookmark: 10.1109/ATS.2000.893643

Authors

I. Pomeranz, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
S.M. Reddy, Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

Reducing test application time for full scan circuits by the addition of transfer sequences

Authors

Abstract