Abstract
Chips with defects, which escape the test, will cause a quality problem and will hurt goodwill and decline revenue. It is important to look for the defect root causes and to derive the prevention strategy. In this paper a case study of a 64M-DRAM is used to demonstrate the approaches of failure analysis in silicon debug stage and, consequently the determination of the tests for production. The consideration of test derivation is both to enhance the yield and to improve the product quality with low test cost. The root cause, electrical modeling of defects, test selection and guardband determination are introduced. Finally, a quantitative measure is given to show the value of failure analysis for a high volume DRAM product.