Software-Based Delay Fault Testing of Processor Cores

Virendra Singh; Michiko Inoue; Kewal K Saluja; Hideo Fujiwara

doi:10.1109/ATS.2003.1250785

2003 Test Symposium

Software-Based Delay Fault Testing of Processor Cores

Year: 2003, Pages: 68

DOI Bookmark: 10.1109/ATS.2003.1250785

Authors

Virendra Singh, Nara Institute of Science and Technology and Central Electronics Engineering Research Institute
Michiko Inoue, Nara Institute of Science and Technology
Kewal K Saluja, University of Wisconsin-Madison
Hideo Fujiwara, Nara Institute of Science and Technology

Abstract

This paper presents a software-based self-testing methodology for delay fault testing. Delay faults affect the circuit functionality only when it can be activated in functional mode. A systematic approach for the generation of test vectors, which are applicable in functional mode, is presented. A graph theoretic model (represented by IEGraph) is developed in order to model the datapath. A finite state machine model is used for the controller. These models are used for constraint extraction so that the generated test can be applied in functional mode.

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Software-Based Delay Fault Testing of Processor Cores

Authors

Abstract

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