On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli

Xiaobing Shi; Nicola Nicolici

doi:10.1109/ATS.2014.30

2014 IEEE 23rd Asian Test Symposium (ATS)

On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli

Year: 2014, Pages: 107-112

DOI Bookmark: 10.1109/ATS.2014.30

Authors

Xiaobing Shi
Nicola Nicolici

Abstract

Post-silicon validation plays a critical role in exposing design errors in early silicon prototypes. Its effectiveness is conditioned by in-system application of functionally-compliant stimuli for extensive periods of time. This is achieved by expanding on-the-fly randomized functional sequences, which are subjected to user-programmable constraints. In this paper we present a method to extend the existing work for on-chip generation of functionally-compliant randomized sequences with support for sequential constraints.

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On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli

Authors

Abstract

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