2016 IEEE 25th Asian Test Symposium (ATS)
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Abstract

This paper presents a novel low cost and double node upset tolerant latch design in 22nm CMOS technology. The latch mainly comprises a single node upset resilient cell which feeds back to a 3-input Muller C-element at output stage. Simulation results demonstrate the double node upset tolerance and an 81.2% area-power-delay product saving for the latch design on average.
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