Abstract
Built-in-self-test (BIST) is a useful technique for memory testing, but the synthesis of memory BIST controllers for 3D ICs (three-dimensional ICs) has not been well studied. In this paper, we propose a two-stage approach to synthesize the memory BIST controllers of a 3D IC under power constraints: the first stage performs memory grouping and the second stage performs test scheduling (including both pre-bond testing and post-bond testing). Compared with the previous work, our approach has the following two advantages: (1) our approach allows a memory BIST controller to perform parallel memory tests; (2) our approach allows a memory test to start from any time point within a session. Thus, our approach has a higher flexibility for both memory grouping and test scheduling. Benchmark data consistently show that our approach can reduce both the test application time and the circuit area overhead at the same time.