A chip-level electrostatic discharge simulation strategy

Haifeng Qian; J.N. Kozhaya; S.R. Nassif; S.S. Sapatnekar

doi:10.1109/ICCAD.2004.1382593

ICCAD 2004. International Conference on Computer Aided Design

A chip-level electrostatic discharge simulation strategy

Year: 2004, Pages: 315-318

DOI Bookmark: 10.1109/ICCAD.2004.1382593

Authors

Haifeng Qian, Minnesota Univ., Minneapolis, MN, USA
J.N. Kozhaya, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S.R. Nassif, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
S.S. Sapatnekar, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

Abstract

This work presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node V/sub DD/ net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.

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